Thejasri Balaraju

1) Working in the Micro Architect Power team, I am responsible for emulation power data generation, analysis, workload-based power modeling and optimization for various graphics benchmark 3D and compute workloads. 2) I analyze graphics block level and chip level power analysis through RTL and architecture level power simulations to drive power efficiency through hardware optimizations by collaborating with architects and designers. 3) Working on Clock gating efficiency analysis and optimization using power tools like Power Artist and PTPX.

• Worked in full chip integration team with major focus on full chip timing convergence, debugging various outliers that contribute to the timing failure and fixing them, caliber checks which ensures quality of the design and also owned structural design of a partition in Full chip. • Provided IO timing constraints for all the blocks in the chip after budgeting for optimal timing convergence. • Execution of full chip timing models based on the block turn ins and providing the impact at full chip level is one of my major responsibilities.

Worked in SOC full chip integration team, with focus on full chip layout, full chip timing execution and convergence.

Trained in all levels and types of software testing. Created test data, test scenarios, test cases, Requirement traceability matrix, Defects log for testing the software quality of a procurement based application. Performed functional testing.