Terry Kang

-. Responsible for developing and implementing cutting edge packaging technology for production; Successfully delivered 1st~5th generations of TPUs (Tensor Processor Unit) for AI, VPUs (Video Processor Unit), Network chip and On-board Optic packaging solutions to data centers. -. Direct advanced packaging technology exploration and development covering 3D, 3.5D, 2.5D, CoWoS-S, -L, -R and Intel EMIB for ultra large packaging and interposer sizes. -. Drive packaging technology decisions through early engagement in chip architecture exploration, floorplan definitions and system technical requirements to enhance chip/package/system co-design. -. Lead the balancing of technical trade-offs among signal, power, thermal, and mechanical requirements to enhance AI system performance and reliability. -. Responsible for a streamlined packaging technology roadmap for TPUs, VPUs, and network chips, aligning cross-functional teams and accelerating product development timelines. -. Built a robust chip packaging team from scratch, encompassing expertise in packaging technologies, signal/power integrity, thermal and mechanical reliability.

• Responsible for 2.5D Si interposer package development: GPU+Memory for high-end GPU • Decided package design rules, interconnection process, assembly flow and materials to meet package reliability and performance requirements for high volume production • Coordinated and managed multi functional suppliers, wafer foundries, OSATs, memory suppliers and packaging material suppliers (Substrate/UF/TIM...) for advanced package technology developement • Successfully developed AP+Memory MCM (Multi Chip Module) package for in-vehicle infotainment system • Successfully developed GPU/Memory MCM and transferred to high volume production for multi million selling gaming console

• Managed/directed advanced flip chip technology development teams and interfaced with customers for technical engagement • Established flip chip package development roadmap based on the understanding of flip chip technology trend and technical challenges related with ELK, lead free bump, Cu pillar, large die and fine bump pitch

• Responsible for materials, processes and manufacturability decision for high pin count, large die flip chip package development for new product roll out • Successfully qualified and rolled out 65nm and 40nm flip chip packages for high volume production. Drove 28nm Flip Chip package qualification projects. Key responsibilities were package BOM finalization, assembly process decision and qualification schedule • Actively involved in defining die and assembly process design rules; UBM size, bump pitch, layout & bump height, lid & stiffener design, chip cap pad design decision based on modeling, process DOE and reliability test results • Coordinated multi-cross-functional technical teams for next generation flip chip product rollout and volume production

• Managed package engineering team to develop advanced package solutions, processes and materials in the broad range of projects; Flip Chip package, BGA package stack, ultra thin RF flip chip package, gold stud bumping process, die stacking process and thin die protective coating process/material