TEJITHA VAJRALA
Physical Design Engineer @ Samsung Semiconductor
About
Physical Design Engineer with experience in full-chip SoC implementation experience across high-performance CPU, GPU, and NPU systems at Samsung Semiconductors. Expertise in floor planning, CTS, UPF-based low-power design, STA/ECO closure, and IR/EM signoff. Delivered 20–30% TAT reduction through Python/TCL automation across 50K–80K timing paths. Authorized to work in the United States.
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United States
Semiconductors
ISP Integration, High-Speed Interconnects, Multi-core SoC,, CPU/GPU/NPU, SoC Architecture, Jira, Git, SystemVerilog, Verilog, Perl, TCL, Python (Programming Language), Scripting & Languages, PDN Optimization, Noise-Aware Routing, Crosstalk, IR Drop (Static/Dynamic), Power & Signal Integrity, Retention/Isolation, MaltiVoltage
Experience
Physical Design Engineer
Samsung Semiconductor
United States
Graduate Research And Teaching Assistant
California State University, Fresno
Fresno, CA, USA
Education
California State University, Fresno
Electrical & Computer Engineering
Vasireddy Venkatadri International Technological University
Electronics and Communication Engineering
TEJITHA VAJRALA's Contact Information
Phone
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