Tejinder Singh, Ph.D., MBA
Head of Strategic Marketing @ KLA
About
Executive Summary: I lead the Strategy & Growth for the SPTS Division at KLA. As a technology and business leader, I am passionate about building high-performing teams, driving innovation, and shaping the future of semiconductor technology. With over 20 years of leadership experience in the semiconductor industry, I have held technical and leadership roles at KLA, Applied Materials, Samsung Electronics, and Intel Corporation. I have led cross-functional, global teams, spearheaded multi-million-dollar R&D initiatives, and played a pivotal role in product development, process technology, and business strategy. My leadership philosophy is centered on empowering teams, fostering collaboration, and driving operational excellence to achieve breakthrough results. Key Leadership & Technical Expertise: - Executive Leadership – Proven ability to build, mentor, and scale world-class technical teams, fostering a culture of innovation, collaboration, and continuous improvement. - Strategic Execution – Successfully developed and implemented global product strategies, leading to strong revenue growth and competitive market positioning. - Technology & Business Integration – Unique ability to bridge engineering and business, aligning R&D efforts with long-term strategic and financial goals. - Operational Excellence – Led 20%+ productivity improvements through talent optimization, streamlined workflows, and enhanced decision-making processes. - Semiconductor Expertise – Deep technical knowledge across Logic (Leading and trailing edge), Memory (DRAM, NAND, MRAM, PCRAM), Advanced Packaging, and Specialty Semiconductors (CIS, Power, Automotive, IoT, AI, Packaging). - Equipment Technologies - Etch, ALD, PECVD, LPCVD, PVD, Anneal, Implant, Epitaxy, - Silicon Photonics for Quantum Computing and Advanced Packaging - Private Equity & Value Creation – Strong interest in Operational Partner roles, leveraging expertise to drive EBITDA growth and long-term value creation for portfolio companies. I hold an MBA from The Wharton School, where I graduated ranked #1 in my class, earning the prestigious Ben Franklin & Palmer Scholar awards. Combined with my Ph.D. in Engineering and leadership experience at Intel, Samsung, and Applied Materials, I bring a unique blend of technical depth, business acumen, and executive leadership to any organization.
United States
San Francisco Bay Area
Semiconductors
C-Level, Presentations, Mass Production, Semiconductor Engineering, Technology Leadership, Driving Results, Product Requirement Definition, Customer Presentations, Data Analytics, Product Differentiation, Analytical Skills, Data Analysis, Business Analysis, Technology Roadmapping, Product Road Mapping, Engineering, Negotiation, Leadership, Cross-functional Team Leadership, Product Requirements
Experience

Chief Technology Officer
San Jose, California, United States
- Leadership & Team Building: Lead a large team engineers across mechanical, electrical, software, process, and productivity disciplines, driving technology and product development for advanced semiconductor manufacturing. - Technology & Product Innovation: Lead the development and commercialization of ALD solutions for logic, memory, and advanced packaging, ensuring performance, differentiation, and cost efficiency. - Business Growth & Expansion: Developed and implemented Eugenus’ technology roadmap, aligning R&D initiatives with business goals, leading to expansion in Asia and the USA. - Revenue Impact: Co-worked with Business team to drive 100% revenue growth in <18 months of joining Eugenus and achieved first year of profitability. - Commercialization & Product Launches: Successfully launched new ALD products, prioritizing differentiation and accelerating go-to-market strategies, fueling business growth across Asia & the USA. - Strategic Organization: Implemented a 3P strategy (Product, Process, People) and restructured the organization into Product Units and Core Technology Centers, defining clear roles and responsibilities. - Customer Engagement & Partnerships: Established strategic collaborations with leading Memory & Logic Foundries, expanding Eugenus’ market reach and technology portfolio. - AI Initiatives: Drove AI initiatives at Eugenus that led to development of AI Research Assistant & Digital Twins - Executive Communication & Board Engagement: Provide quarterly updates on technology development, business growth, and talent strategy to the board, ensuring alignment with corporate objectives. - Technology Roadmap Leadership: Oversee the bi-annual semiconductor technology roadmap across Advanced Logic, DRAM/3D-DRAM, 3D-NAND, and Advanced Packaging, shaping Eugenus’ long-term innovation strategy. - Sustainability & Net Zero Commitment: Established a Net Zero playbook, driving a 50% reduction in Scope 1 & 2 emissions for Eugenus products

Director, Products & Technology
Santa Clara, California, United States
Managed a Product Portfolio in the Speciality Semiconductor Segment (iOT, Communication, Automotive, CIS, Power) and Emerging Memory (MRAM, PCRAM). ● Director of Products for the 300mm ICAPS Business ● Developed & maintained a wide customer base and established preferred strategic partner leading to revenue growth ● Prepared Quarterly Business Review (QBR), Strategy Review (SR), Red Team Analysis ● Drove initiative to invest in a distributed lab strategy for Research, Development & Engineering. ● Collaborated with cross-functional teams such as Engineering, Manufacturing, Process, and Sales to develop new and enhance existing products: Plasma Etch, CVD, PVD, ALD, LPCVD, Epitaxy ● Developed solutions for Advanced Packaging and Quantum Computing using Silicon Photonics. ● Led a team of engineers to develop a novel film stack in Extreme Ultraviolet Lithography (EUV) that reduced EUV dose by >30% with potential cost saving of $1B+. ● Improved organizational productivity by 20% through automation, established new tools for engineers, streamlined talent acquisition, and accelerated time to effectiveness for multiple job roles. Key Device Technologies: Logic, DRAM, NAND, CIS, Power Semiconductor, Advanced Packaging, Photonics

Global Product Manager
Santa Clara, California
Managed 300mm Product Portfolio (PVD, CVD, Etch, LPCVD) in the Specialty Semiconductor & Emerging Memory market (MRAM, PCRAM). Leading next generation of Patterning technology for Semiconductor industry (Logic & Memory applications). Expertise in EUV process development for 36nm and sub 30nm pitch nodes. Resolved EUV Stochastics issues using a cutting edge Etch and Deposition technology. Developed a novel integration approach for DRAM active cut.

Senior Engineer
Hwaseong, Gyeonggi-do, Korea
Logic 7nm EUV Etch Process Development. - Research & Development of Logic 7nm Back-end-of-line (BEOL) Etch process. - Process & Equipment development for technologies beyond Logic 7nm . - Improved electrical and defect yield from 0% to >95% for BEOL EUV Via layers.

Senior Process TD Engineer
Hillsboro, OR
- Process Technology Development Engineer with an extensive experience in Plasma Etch process development (22nm and 14nm), equipment maintenance and troubleshooting. - Mentored and trained Process Engineers, Engineering Technicians and Manufacturing Technicians on sustaining, development and Ramp of 22nm and 14nm technologies. - One of the lead Engineers to transfer technology to virtual factory and Best-in-Class matching. - Technical leader in Back-End of Line Process Development with a specific focus on Plasma Etch processes. - Strong problem solving skills and excellent at root cause identification for equipment troubleshooting, defect reduction, yield improvement, cost reduction and Operations.

Research Assistant
1) Silicon Thin Films: • Researched, analyzed, and resolved outstanding issues in plasma-enhanced chemical vapor deposition (CVD) of amorphous silicon (a-Si:H) thin films, allowing the design of systematic strategies to optimize film properties: • Established the growth mechanism of a:Si-H thin films that fully explains experimental data, using density functional theory (DFT), Molecular-dynamics (MD), and kinetic-Monte Carlo (KMC) simulations. • Modeled, characterized, and determined structure-property relationships of a-Si:H thin films, enabling better performance of electronic and photovoltaic devices. 2) Carbon Nanotubes • Analyzed and modeled hydrogen plasma exposure of multi-walled carbon nanotubes (CNTs) to enable potential applications of CNTs in hydrogen storage devices: • Elucidated the H-induced transitions of CNTs to diamond nanocrystals using DFT and MD simulations resulting in new recipes to synthesize diamond crystals at the nanoscale. • Established a novel allotrope of carbon and characterized new carbon nanostructures. Validated with Transmission Electron Microscopy (TEM), Raman spectroscopy, and Electron diffraction. 3) Compound semiconductor nanocrystals • Synthesized and characterized doped colloidal semiconductor nanocrystals (quantum dots of ZnSe & ZnO) that have applications in nanoelectronics, spintronics, and solar cells: • Explained the fundamental doping mechanism in nanocrystals based on a novel surface kinetic-growth model. Proposed novel experiments toward optimal design of doped quantum dots. • Designed and developed a novel optimization scheme based on simulated annealing. Implemented this technique to successfully local global minima of the structures of compound semiconductor clusters.

Technical Intern
Raschig Gmbh, Germany
Ludwigshafen Am Rhein, Rhineland-Palatinate, Germany
Research Intern
Education
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