Tao Lu

Working on the hardware simulation/emulation and software-system integration (SSI) for the next generation AI accelerator TPU. Group of Chip Implementation and infrastructure (CI2) under Google Cloud.

Work on the next generation of ZKP hardware. RTL design and verification.

My research focus on Domain-specific Accelerators. We applied parallelism techniques at micro-architecture level and implemented on FPGA using RTL and HLS. SCU: A RISC-style heterogeneous architecture for blockchain acceleration • Designed a heterogeneous architecture to accelerate the processing of blockchain (Ethereum). • Designed an innovative RISC-V-like ISA to replace the Ethereum stack-based inefficient EVM model, implemented by a hardware runtime interpreter. • At the micro-architecture level, leveraged Instruction-level parallelism (ILP), out-of-order (OoO) pipeline, register renaming and TLP to remove bottleneck. • Implemented the RTL design using SystemVerilog and evaluate it on Xilinx FPGA via Vivado/Vitis toolchain. BPU: Hardware-based Blockchain Processor on Smart Contract Execution • Designed the first hardware-based accelerator for blockchain processing by leveraging instruction-level parallelism (ILP), transaction-level parallelism (TLP), and data flow optimization. • Implemented on a Xilinx FPGA kit using Verilog and High-level synthesis (HLS C++). • Performed behavioral data analysis using Python. Developed a series of tools analyzing raw data from Ethereum history and traced the execution of smart contracts. • Published this work at a top-tier conference, the 57th ACM/IEEE Annual Design Automation Conference (DAC) 2020.

Another focus of my research is blockchain-based applications. I contribute to one COVID-19 related project funded by NIH and another project combining blockchain and machine learning. GeauxTrace: A blockchain-based contact tracing platform for COVID-19 • Designed and implemented a blockchain-based contact tracing platform using a unique global tamper-proof contact graph. Published this work in BDCAT 2022 (<30% acceptance rate). • Individually developed the first prototype, including private blockchain using Ethereum, an Android app (Kotlin) using BLE and a server backend (JavaScript). • Headed a team of five undergrad developers and managed the project including feature design, code review, GitHub organization and App releases (Google Play & Apple Store). • This project is based on my blockchain research and got fully funded by NIH (success rate: 29%) in collaboration with other PIs, reported by national news outlets such as Yahoo and USNews. iChain: A Blockchain-Based Computation Trading Platform for Machine Learning • Designed and implemented a DApp/Smart contract on the Ethereum blockchain, which connected the computation demand and supply in the machine learning training market. • Initiated and built the minimum viable product (MVP), including a front-end website (Javascript), a command line interface (CLI), and setting up a back-end blockchain system. • Actively led a team of four undergraduate students, applied Agile Development and project management skills, presented industrial and academic innovation to the group once a week, and planned and administered the roadmap.

• Taught 20 undergraduates in a Micro Processor Lab in Fall 2017, received an evaluation of 3.3/4 (average 2.9). • Taught 25 undergraduates in an FPGA Lab during Spring 2018. Gave a 15-20 mins lecture per class to improve the teaching quality under difficult conditions, which elevated my evaluation score to 3.5/4.

This work focused on an advanced FPGA-based blockchain accelerator for Hyperledger Fabric. • Developed a large-scale FPGA-based blockchain accelerator targeting Hyperledger Fabric with a team of five. Worked remotely with multicultural colleagues from China, Singapore, and San Jose due to the pandemic. • Verified the RTL design (in SystemVerilog) on Xilinx FPGAs using Vivado and developed testbenches and TCL scripts. • Helped develop software to offload the burden of network transferring using Go and tested using Python scripts. • Successfully presented the phased progress to the heads of the company including Xilinx CTO on behalf of the team.

Contribute to developing a consumer electronic small device funded by indiegogo. • Designed a BLE-based vehicle collision alert system in four months from sketches. Performed PCB design using OrCAD • Designed the power solution using the rechargeable battery and evaluated the product in the lab and in daily conditions. • Searched ICs, made the bill of materials (BOM), and followed up with third-party manufacturers throughout the process to check the quality and supply.

I'm doing research on computer engineering and domain-specific acceleration. My major works are focusing on designing accelerator for blockchain applications, and published on top tier conferences.

Learn programming, system design and analysis in UCLA extension programs, filling my gap time.

Graduated with MSEE degree, focused on VLSI, chip design and verification area.