TAMILAN ELANGO

TAMILAN ELANGO

Signal and power integrity @ Valeo

About

 Signal and Power Integrity and reliability Engineer with 7 Years of Experience in Simulation, Reliability and PCB like Automotive Aerospace, Telecommunication, Mobile Industry and Defense Applications. Perform Pre-Layout &Post-Layout simulations Extraction of S-parameter models using 2.5D, 3D solvers. Frequency Domain simulations (IL,RL,FEXT,NEXT) and Perform Time Domain (TDR) S-parameter extraction of Board to analyze Insertion loss and Return loss. PKG analysis for violations like passivity, reciprocity & causality. SI simulations of different types of DRAM with different chip sets using HSpice or Mobile, Enable Pre-Emphasis for DRAM, Enable Equalization in Read &Write Modes for LPDDR5X.Vref training for Read & Write, CA waveforms Implement JEDEC specifications for different DRAM standard/configuration Eye diagram analysis in Read &Write Modes of DRAM for Aperture, Noise Margin, Reflection &Crosstalk issues. Analysis of different types of DRAM for different simulation setup conditions Familiar with Differential Via modeling and impedance optimization techniques. Work with DRAM vendors for possible solutions to failures observed in SI simulations. Hands on experience on S-Parameter extraction using cadence Sigrity, Ansys HFSS 3D Layout tool, SERDES, IR Drop and LPDDR4 and LPDDR5x batch Simulation for signal integrity validation. Hands on experience on DC Drop analysis, Loop inductance, Decoupling and optimization. Experienced in using IBIS (RLC & Comp), IBIS-AMI model parameters, Touchtone, Spice model simulation Board level simulation for signal traces to extract system performance parameters such as eye- diagram, Jitter etc Support Global Customer Engineering Team to resolve the issues seen in customer layout simulations Designed Multi-layer printed circuit boards. Designed up to 20layers, using latest technologies. Crosstalk and Reflection analysis for different interfaces Experience Requirements analysis, stack-up validation &PCB material selection for high speed design and capability of working with the layout team. Have Worked PCB Design like Cadence16.6&17.4, Altium Designer 20.0.9 and Development of Analog, Digital, RF & Mixed mode. Have Good Knowledge on placement and routing of RF, DDR3 /DDR4, PCIe, RGMII, BACKPLANE, USB3.0, JTAG & HDMI interfaces, Ethernet and minimize EMI/EMC issue in Power section. Good knowledge on stack up development for impedance and setting up various specific design constraints for fine pitch components and entire board

Country

India

City

Bengaluru

Industry

Electrical & Electronic Manufacturing

Skill

signal integrity and power integrity , Cadence Software, Digital Hardware Design, Altium, OrCAD Capture CIS, Computer-Aided Design (CAD), EDA, LabVIEW, SPICE, Management, Microsoft Excel, Project Management, Engineering, PCB Design, AutoCAD, Electronics

Experience

Valeo

Signal and power integrity

Valeo

LinkedIn
2023-4 - Present · 3 yrs 6 mos

Tamil Nadu, India

SIPI SIMULATION ENGINEER

Cyient

Hardware Design & Signal and power integrity engineer

Cyient

LinkedIn
2021-11 - 2023-4 · 1 yr 6 mos

India

Wuerth Elektronik India Pvt. Ltd

Printed Circuit Board Design Engineer

Wuerth Elektronik India Pvt. Ltd

LinkedIn
2019-2 - 2021-11 · 2 yrs 10 mos

Karnataka, India

MultiTech-EDA Systems Pvt Ltd

Hardware Design Engineer

MultiTech-EDA Systems Pvt Ltd

LinkedIn
2017-1 - 2019-1 · 2 yrs 1 mo

BANGALORE

BANGALORE

Education

Adithya Institute of Technology

Adithya Institute of Technology

LinkedIn

Electrical and Electronics Engineering

2012 - 2016 · 4 yrs

TAMILAN ELANGO's Contact Information

Email

******@***.com

Phone

(**) *** ****

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