Takashi Nakagawa
Senior RTL design engineer @ Intel
United States
Folsom
Semiconductors
ASIC, FPGA, SoC, VLSI, Verilog, RTL design, Logic Synthesis, AMBA AHB, AXI, Functional Verification, Mixed Signal, Integrated Circuit Design, Static Timing Analysis, ARM, SystemVerilog, RTL Design, Semiconductors, Embedded Systems
Experience
Senior RTL design engineer
Intel
Folsom CA
GPU RTL design at VMI. Stereo correlation processor RTL design at PerC.
VP of Engineering / Board of directors
Strauss Technology, Inc
Santa Clara, CA
Designed Perspective/Affine transform engine, OpenVG core, etc... Strauss Technology, Inc closed business in 2013. --------------------------- Applause Technologies, Inc is renamed to Strauss Technology, Inc. as of April 2010. We are developing high performance graphics engine core as IP or ASIC.
VP of Engineering / Board of directors
Applause Technologies, Inc.
Sunnyvale, CA.
Co-Founded graphics processor design company. https://segaretro.org/Advanced_Pico_Beena https://ja.m.wikipedia.org/wiki/アドバンスピコ・ビーナ
Design Manager
Arcadia Design Systems
San Francisco Bay Area
Designed high performance CPU, graphic processor, audio signal processor, ...
Senior Design Engineer and Group Leader
Giga Lex
Osaka, Japan
Designed Digital Video LSI and DSPs by VHDL
Project Manager
transcosmos inc.
Tokyo, Japan
Project manager for Real Audio
Technical support engineer
KLA
Yokohama, Kanagawa, Japan
Staff engineer
Panasonic North America
Osaka, Japan
Developed Digital Audio Tape recorder and Professional Digital Video Tape recorder (D-3, D-5) at Audio Video Research Laboratory.
Education
Keio University
Digital Signal Processing
Keio University
Takashi Nakagawa's Contact Information
Phone
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