Suraj Gajendra

As a Board Member of the Autoware Foundation, I support one of the world’s leading open-source initiatives advancing autonomous driving through a shared, production-grade software stack. Autoware’s work in developing open, modular, and increasingly foundation-model–driven autonomy platforms is critical to accelerating innovation, improving safety, and lowering barriers for OEMs, robotics developers, and mobility providers. My involvement leverages my experience in scalable compute platforms, software ecosystems, and industry collaboration to help guide strategy, foster cross-industry partnerships, and ensure that open, interoperable autonomy frameworks become a cornerstone of the Physical AI era.

As the founding Chairperson of the SOAFEE consortium, I helped establish and lead a global industry collaboration that is accelerating the transition to software-defined vehicles and edge compute platforms. SOAFEE brings together OEMs, silicon providers, cloud companies, and software leaders to create a standards-based, cloud-native architecture that enables scalable, safe, and continuously updatable automotive and robotics systems. The consortium’s rapid growth and industry adoption reflect the collective strength of its members, and I’m proud to contribute leadership that aligns ecosystem partners, drives technical direction, and helps translate shared vision into deployable solutions.

Back at Arm, I lead the Products and Software organization at Arm focused on the rapidly expanding Physical AI market spanning automotive and robotics—an industry projected to exceed $1T+ this decade as intelligence moves from the cloud into autonomous machines. Arm’s scalable compute, safety-certified architectures, and software ecosystem power the majority of automotive and edge-AI silicon, enabling energy-efficient, real-time decision making at scale. In my role, I drive product and software strategy that helps OEMs and robotics innovators bring safe, intelligent, and software-defined machines to market faster, making Arm a foundational platform for the next generation of autonomous systems.

Led the AI Strategy and Product Management teams for Xeon CPU and Xe GPU product lines together accounting for over $3B in AI revenue annually for Intel. AI is a heterogeneous workload, ie. Some use-cases not just run efficiently on a CPU but the CPU is the most cost-effective hardware for them. For example, Inference, classical ML, small-scale training, fine-tuning and transfer learning. However, use-cases such as large scale training and deep-learning need specialized parallel compute engines such as GPUs and DL accelerators. So, its super critical for semiconductor companies in this space to invest not only in enabling the right AI features across all their heterogenous compute hardware but also in having a robust foundational software infrastructure to access them. My team was accountable for leading this for Intel Xeon and Xe GPU product lines. AI market is expected to be >$200B growing at over 30% CAGR by 2025 across key markets such as Financial services, Healthcare, Consumer, Media, Manufacturing and Automotive. While the semiconductor or hardware share will see a modest growth, its the AI applications and services that is fueling the exponential growth. Data Scientists and AI developers enabling these applications and services expect a development environment that can offer them flexibility, openness, performance and is hardware agnostic, where they can just focus on building AI applications on data-sets that can massively improve productivity for end-users or processes. With complete ownership of Business/Product strategy and Execution, my team is focusing on enabling such a versatile cloud-native environment using not only Intel's foundational software assets and tools like OneAPI, OpenVINO, BigDL, CNVRG.io etc but also our ISV partners's and those available in open-source ecosystem. Its paramount to get this right to unlock AI's full potential for the masses.

I led the Technology Strategy & Architecture group for Arm's Automotive and IoT business, enabling Arm's HW & SW solutions for the AI powered future. • Responsible for delivering consistent HW and SW solutions roadmap based on Arm’s heterogeneous compute IP portfolio working cohesively with Arm's strong central engineering and vast external partner ecosystem. My team was also responsible for strategy and roadmap definition for foundational technologies such as Functional Safety, Cyber-Security, and Machine Learning across Arm Cortex-A, Cortex-R, Cortex-M CPU product lines, Mali ISP, and Ethos ML accelerators specifically in the Automotive and broad IoT segments accounting >$500M revenue annually for Arm. • AI-driven Autonomous decision-making is going to be the predominant workload of the future; This is a rapidly evolving space with major technological breakthroughs shaping our future every day and for Arm, an opportunity to scale our current Automotive and IoT business multi-fold. I led the strategic direction for Arm in this space building strong coalitions and partnerships in the industry, working together to drive a collective direction with help of initiatives such as… - Through SOAFEE strategy along with our key partners, led the team that delivered a Software framework targeting Cloud-Native development environment for the Software-Defined Vehicle of tomorrow (soafee.io) - First Arm HPC-based AVA developer platform for software-defined systems workload development on Arm. Enabling a true Arm-on-Arm development opportunity for SDV and Automotive market. - Through Sparta program, established a robust strategy for Arm to make maximum impact in the evolving AI driven use-cases in Automotive.

Awarded the title of Intel Principal Engineer for all the technical contributions over the years in the field of microprocessor definition and architecture for Internet of Things Industry. Accountable for vision, business strategy, product definition and execution of Atom microprocessor product line targeting broad spectrum of IoT markets. Defined 6th Gen Intel Atom Microprocessor x6000E (Code named "Elkhart Lake") from scratch on a blank sheet of paper targeting the intelligent edge applications across IoT markets such as automotive, industrial automation, retail, consumer electronics etc.. This was Intel's first ever product built specifically for the IoT market. Led cross-functional team with over a $100M investment from product's conception all the way through to tape-out. Was responsible for all customer engagements across the above mentioned markets owning decision making on product feature requirements, IP selection/licensing, market expansion, product cost optimization and Go-To-Market strategy with a target of >$2B revenue @ over 35% OM. Elkhart Lake was successfully launched in 2020 and is an active revenue stream for Intel since then.

Responsible for systems architecture of Intel ATOM Microprocessors/ASSPs targeting key IoT markets like Industrial Automation, Automotive, Retail, Smart Home, Office Automation etc. focusing following technologies... - Time-Sensitive compute, bus architecture and Real-Time system performance - System-level Industrial & Automotive time-synchronization protocols like TSN, PCIe PTM - Deterministic Ethernet and Field-bus protocols - Device and system-level security features/solutions - Machine Learning and Vision-based analytics - CPU and IO Virtualization - Reliability and Functional Safety - Audio and Speech acceleration - Wireless connectivity protocols - Automotive IVI and Telematics

Key focus area: SoC active and stand-by power optimization for key battery-life use-cases on PC, tablets and phones taking full benefit of Intel's 64-bit multi-core SoCs built on advanced industry-leading semiconductor process nodes. Drove multiple power optimization techniques on commercial OS like Windows, Android and Chrome for Intel SoCs. Led unique use-case driven power and performance (PnP) optimization on new product areas like the Wearables and IoT, where not only PnP is paramount but the use-cases are completely different compared to traditional compute devices mentioned above. Pushed SW/FW driven low-power techniques to compliment power management features offered by IA across key compute engines like CPU, GFx and Image processor to make efficient use of common resources such as memory, display and connectivity sub-systems.

Managed Memory cluster Post-Si validation team working on multiple Atom products. The team drove key memory technology enabling for Intel D2500 Atom SoC in particular, highlight being the DDR3L introduction on 32nm providing 22% power savings.

DDR2/3/3L and LPDDR2/3 memory interface design and Post-Si validation on 65/45/32/22nm supporting datarates from 400Mtps to 1600Mtps - Involved in all aspect of PHY design including RTL, Circuit Design, Layout and Post-Si - Led the development of memory reference code and initialization sequence including training algorithms for key Intel Atom SoCs. - Drove key power saving design changes in DDR3 Phy gaining significant battery life improvements thereby enabling Intel to maintain the ASP on Core I3/I5 product lines in 2009. - Led DDR3x/LPDDRx Post-Si validation and Firmware development for multiple Intel ATOM SoC designs across various product segments including Phones, Tablets and Micro-servers. Intel Global Power team involved in power optimization initiatives. - Developed power estimation, measurement and benchmarking tools & processes - Co-chaired cross-product work-group leading multiple design initiatives on Memory Technologies. - Competitive analysis of DDR/LPDDR designs in terms of area, power and performance. Small and Large signal Memory design @ 45/32nm Intel process nodes - Developed low power 6T-SRAM memory blocks for core I7 processors. Key contributor for low-power design and validation on an Integrated Sensor Hub project - Drove the design of validation platform for an Intel sensor hub IP - Gained significant knowledge in Sensor Hub ecosystem including the general pupose IO technologies like I2C, I2S, SPI and UART.

Bangalore