Sujith Kaiprath Veettil

Staff GPU Design Verification Engineer @ Qualcomm

About

GPU Verification Engineer, currently verifying Shader Core/Processor and Ray Tracing Unit (RTU) Accelerators for next-gen GPUs. Computer Engineering graduate from North Carolina State University specialized in ASIC Design and Verification, and Computer Architecture.Previous experiences include Functional and Formal verification of RISC-V processors, DSP blocks and Main State Machines(MSM) at Cirrus Logic Inc using SystemVerilog and UVM based test benches. Owned multiple block, subsystem and chip level assignments.Programming Languages: Verilog, SystemVerilog, C/C++, PythonTechnical Skills: UVM, RTL, Object Oriented Programming (OOP), Logic Design, Linux, Computer Architecture, VLSI, Human-Computer Interaction, SoC, RISCV, GPUTools: Questasim, Synopsys Design Compiler, Cadence Indago, Simvision, Verdi, Jasper Gold

Country

United States

City

Austin

Industry

Semiconductors

Skill

Generative AI, SIMD, GPU, Shader Processor, Computer Graphics, Ray Tracing, Program Coordination, Team Coordination, DV, Universal Verification Methodology (UVM), SystemVerilog, Verilog, ASIC Design, System on a Chip (SoC), Object-Oriented Programming (OOP), Project Management, Machine Learning, Artificial Intelligence, Agile Methodologies, Digital Electronics

Experience

Staff GPU Design Verification Engineer

Qualcomm

2024-7 - Present · 2 yrs 3 mos

Austin, TX

» GPU Shader Core Verification - Unified Shader Processor. » Ray Tracing Unit(RTU) Accelerator Verification. » Shader Processor(SP) Performance Counter Verification. » Architected and developed scalable and flexible UVM testbenches from scratch. » Mentored engineers on testbench implementation while also teaching System Verilog concepts, UVM methodology, good coding practices, etc. » GenAI in Verification.

Senior Design Verification Engineer

Cirrus Logic

2023-4 - 2024-7 · 1 yr 4 mos

Austin, Texas, United States

» Verification of RISC-V processor subsystem using both functional and Formal verification (using Jasper Gold). » Verified the Core-Local Interrupt Controller (CLIC) at the block level, and also validated its integration with the RISC-V CPU core. » Created and executed comprehensive verification plans and schedules for digital and mixed-signal blocks across multiple chip projects from block to full chip integration level and Gate-Level simulations. » Developed GUI tools and scripts for process improvements/automation.

Design Verification Engineer

Cirrus Logic

2019-7 - 2023-3 · 3 yrs 9 mos

Austin, Texas

Responsible for functional and formal verification of digital and mixed-signal SoC/ASIC/IP. Skills: » Verification Planning » UVM based Testbench development » Constrained Random stimulus generation » Scoreboard development » Assertions » Functional Coverage » Failure analysis and bug tracking » Gate Level simulations (GLS) » Formal Verification

Digital Design Engineer Co-op

Analog Devices

2019-2 - 2019-5 · 4 mos

Greensboro, North Carolina

Design Verification Engineer Intern

Analog Devices

2018-5 - 2018-8 · 4 mos

Greensboro, North Carolina

Student Coordinator at Committee on International Programs (CIP)

North Carolina State University

2017-8 - 2018-5 · 10 mos

Raleigh, North Carolina

• I worked as the Graduate Student Coordinator for the Committee on International Programmes (CIP). • Provided services in scheduling and organizing events for International students and exchange researchers and faculties. • Was part of the committee for evaluation of research proposals and works of International student scholars.