sudhir jain

I am a committed physical design (PD), synthesis, and static timing analysis (STA) engineer with 25+ years of progressive leadership experience. Leverage leadership, EDA tools, automation, and scripting skills to complete multiple projects from 250nm to latest technologies, meeting schedule, area, power, timing, and Design for Manufacturing (DFM) goals. Handle synthesis, DFT insertion, formal verification, low power insertion, floor-planning, placement, CTS, routing, timing optimization, SI, timing closure, signoff STA, functional ECOs, EM, DFM, DRC, and post-silicon support to maximize PPA. MY CORE COMPETENCIES Synthesis, PNR, Low Power Implementation, Constraints Generation, STA, Eco Closure, Timing Signoff, PNR Signoff, ECOs, CAD flows and Methodologies, Post-Silicon Debug Scripting Languages: Perl, TCL/TK, Python EDA Tools: Synopsys (DC, PT-SI), Cadence (RC, LEC, CLP, Encounter, QRC, ETS), Mentor Graphics (Calibre), Dorado design automation (tweaker), IBM EDA, Data Analysis (Tableau, Pandas)