Srimannarayana Reddy Y.

As a Design Verification Intern at Cadence Design Systems since June 2025, contributed to advanced verification workflows using Cadence JasperGold across multiple high-performance PCIe PHY projects. Performed comprehensive formal verification, including CSR verification using the JasperGold CSR App to ensure correctness of register definitions, access policies, and reset behaviors. Executed low-power verification using UPF, validating isolation logic, retention strategies, and power-switch functionality. Conducted connectivity verification to ensure accurate signal mapping and hierarchical integrity across modules. Additionally, developed formal checkers for FSM verification using the Jasper FPV App and carried out lint, DFT, and automated formal checks using the Jasper SuperLint App.