sriharsh pakala

Emphasis on developing novel circuit techniques for low-power, area-constrained integrated power management blocks.

⇒ Responsible for project management and technical liaison for clients and subject-matter-experts. ⇒ Performed technology and IP evaluations, assessed conceptual prototypes and formulated product development recommendations. ⇒ Performed pricing and distribution analysis for new niche products based on scaling and financial constraints.

Implemented a VGA controller using MATLAB and Verilog coding through Xilinx Integrated Software Environment (ISE) suite on Spartan II prototyping board.

Design and verification of an on-chip clock generation block. Responsible for definition of block-level specifications and transistor-level design. Verified functionality across PVT corners through AMS and spectre simulations. Performed transistor-level design, Verilog coding, Monte Carlo simulations, behavioural modeling and guided layout.

Initiated the process of procuring proprietary 130 nm IBM design kit (PDK) for installation to the Cadence (virtuoso) tool suite.

⇒ Integrated Power Management Circuits: curriculum expansion, lecture material creation, course instruction. ⇒ Digital VLSI Design: Lab instruction, project design, and grading. ⇒ Analog VLSI Design: Part-time course and lab instruction. ⇒ AC and DC Circuits: Part-time course and lab instruction for an undergraduate (sophomore) level core course.

Analog IC Design Intern at Power Management IC Group of QCT. ⇒ Developed a substrate modeling methodology for quantifying dominant coupling mechanism. ⇒ Investigated isolation structures for mitigation of phase noise degradation in XOs. ⇒ Assisted in the design of novel differential crystal oscillator (XO) structures for next-generation chip IP.