Sreenivas Subramoney

Working on AI datacenter GPU scale-up and scale-out for products beyond Feynman

Established and led the Processor Architecture Research (PAR) Lab on Intel's global research into advanced CPU architectures and core microarchitectures to extend Intel’s general purpose computing leadership. ~1/3rd of Intel P-core's generation-to-generation performance for multiple server and client product families were delivered based on fundamental microarchitecture breakthroughs in data prefetching, instruction delivery, branch prediction and predication, memory disambiguation, energy-efficient renaming, value prediction and criticality-driven speculative techniques. Researched and built accelerator-subsystems for future NPU architectures for emerging AI use cases on client systems. Developed memory-centric GPU architecture proposals for generative AI. Researched and developed multiple technologies for TCO-optimized tiered-memory systems for future Xeon servers . Established and was Technical PI of the Foundational Microarchitecture Research (FoMR) research center, jointly funded by Intel and the National Science Foundation (NSF), comprised of 20+ University research groups across the USA (2018-23). Established and was Technical PI of the Intel Transformative Server Architectures (TSA) research center spanning USA, Canada, Europe, and Israel (2022-25). Member of the world-wide IEEE/ACM ISCA Hall of Fame: ISCA is the premier forum for new ideas and research results in computer architecture, and of the IEEE/ACM MICRO Hall of Fame: MICRO is the world’s premier venue for microarchitecture research for advanced computing.

Built and led Intel India’s first CPU Architecture team to Intel-wide recognition for its central contributions to Intel’s CPU product roadmap. Established tight collaboration with Intel’s flagship Israel-based CPU Architecture organization and then became part of it. Led the entire SoC/Uncore performance architecture for multiple leadership Client Microprocessor families (Sandy Bridge through Ice Lake) across product segments: ultrabooks, notebooks, tablets, desktops, workstations. Led organization to numerous innovations on caches, interconnects and memory subsystems.

Chartered with developing strategic long-term capability for Intel Architecture platform power, performance, and thermals analysis. Led the development of a breakthrough platform modeling environment for power/performance that became the new de facto standard for the architecture and microarchitecture modeling of all SoC/uncore projects at Intel across client, server, and mobile product lines.

Core developer (one of 5) of Intel’s first Java Virtual Machine (JVM) later to become the Open Runtime Platform (ORP) and the Apache Harmony JVM. Led research at the intersection of CPU (micro)architecture and garbage collection, thread synchronization, type safety, multithread scalability and core VM technologies. Invented several memory management and compilation techniques that synergistically with CPU hardware features improve Java/.NET application performance and scalability, spawning new Intel ISA extensions and managed runtime enhancements shipped as part of ISV products (BEA Weblogic).

Developer of 64-bit server Linux operating system kernel for the Itanium product family in deep collaboration with HP, CERN, IBM, VA Linux, and the Linux open-source community as part of Project Trillian. Designed and implemented IPF Linux Interrupt Architecture, IA64-Linux Driver interface, kernel debugger and CPU hazard detection utilities. Key contributor in 5-person engineering team that achieved first-boot of Linux on Itanium A0 silicon. This led to Andy Grove’s demo of Itanium platform running 64-bit Linux with Apache Web Server at the Intel Developer Forum.

Led Application Engineering teams working on-site at Intel’s key ISV customers like IBM, Microsoft, SGI, Oracle, and Unisys re-architecting their software stacks on Intel® Pentium® Pro, Pentium® II and Pentium® III based multi-processors for performance and scalability; achieved average of 3X performance gains from hardware, application and system software optimizations.