Sreedhar Sampath

Mini SoC Verification lead a team working on Uvm Verification including GPU VIP and CPU ips. Responsibilities Include: - Technical Lead - Architecture discussions and deploy Mini SOC end-end tests. - Testbench development(UVM), Fabric corner cases including at system level - CPU tests at Mini SOC, including power verification. - Functional, connectivity and corner tests including CPU, Coherent and Non-Coherent Interconnect, CPU, Memory controller, PHY, and GPU VIP. - Mini Soc verification, planning, execution for the team

Interconnect Verification • Owned and implemented ACE-based interconnect verification specification. • Wrote the verification specification, which involved several random/constrained random test suites for the complex Interconnect subsystem. • Supported and modified UVM drivers/monitors used in all the tests. • Created UVM sequences extending several tests from the specification. • Wrote many tests to verify some directed scenarios. These were written in constrained random manner with many seeds. • Owned Cadence/Synopsys Integration of VIP’s and used them as master to generate processor traffic and found several issues. Also • used performance analysis tool (IWB) and found critical issues, which led to design changes. • Integrated/modified scoreboard and led the verification environment at the subsystem level and chip level to verify the IP. • Used the C environment to create actual processor traffic and created tests at chip level. • Supervised coherent testcases w.r.t ARM processor. Found issues in integrating ARM A-57 around barrier/DVM area. SOC Verification: • Owned and implemented the UVM environment for the subsystem environment relating to ARM CPU’s. o The environment uses C based tests running on CPU loaded in SRAM, read by the ARM CPU from memory, and executed. • Involved in supporting and modifying UVM drivers and monitors for the testbench portion of the test-bench. • Integrated Cadence VIP for protocol checks and performance analysis; discovered issues on the interconnect. • Found critical problems in integration of CPU and low power design. • Developed UVM -- created a test-plan and implemented several test scenarios. o Designed callbacks and testbench environment to implement features to interact with C environment.

I am leading a team offsite in India as well as some members in US as part of the verification group for a Subsystem in all TI OMAP processors. Also held responsibilities in designing High speed DMA access via OCP core through a USB interface for increase in performance. Key responsibilities held were in areas of spec definition to design, including backend and verification. Verification of subsystems using automation tools such as veriperl with combination of Specman eVC's • Debug Subsystem -- various flavors developed as a regressable, Perl-oriented testbench and test suite and works as a parameter configuration. • Debug Subsystem - Designed architecture for the system level testbench. o This testbench utilizes multiple die2die interconnect and multiple tap links. • Created test plan -- Created specification for the system testbench deployed in Specman. o Created test infrastructure using Specman and standard Specman methodology. o The subsystem design utilizes various flavors of the debug subsystem and several chips.

Part of a team worked on design and verification of IEEE standard cJTAG (compact JTAG). Also was involved in designing trace converter for Debug interface for TI DSP processors. This is in several chips of all DSP processors using the debug mechanism for onchip debug strategy. • Designed hardware accelerators for various performance monitors on various bus protocols. o The hardware accelerator is used to discover architectural design issues regarding latencies and snoop count for memory accesses, applying the accelerators for software codec development and improving codec design. • Designed a verification environment in Specman applicable in several system designs. Design Lead (02/2010 to 08/2010) • Collaborated on the design of STP v2 protocol for a trace solution to execute a global time correlation across all debug solutions. • Supported verification activities for all IP's at the system level. o Designed the test-bench, writing test stimulus, deriving functional coverage, implementing various coverage metrics and leading verification activities for the debug subsystem. • Collaborated on design and complete backend including synthesis, STA and ATPG on the IP.

Worked on High Speed Serial Interface as a design Engineer. Prototyped successfully HSS on a 6M Virtex based FPGA which was strategically used for several other devices like PCIE express. Worked as a designer for HSS and also part of PCIE Express team. Worked on Assertion based verification, systemC, system verilog and formal verification methodologies in verifying different chips.