Soumya Dash
ASIC Design Verification Engineer, Machine Learning @ Google
About
🌟 Problem-Solving Aficionado | Googler | UPenn Alum 🎓 Fueled by a passion for tackling complex challenges during design and verification of chips in a structured way, I thrive on collaboration and treasure meaningful connections. Driven to create impactful things and contribute to standout innovations in the computing world, every step I take pushes me to make a bigger impact than ever. 🚀 Embarking on a quest to blaze my own trail of success while inspiring and empowering others to reach their highest potential. I’m excited to connect with passionate minds from all walks of life, absorbing diverse perspectives and insights. When I’m not geeking out over chips, I’m immersed in the rhythm of financial markets, jetting off on weekend getaways, or indulging in new culinary discoveries. Let’s connect, stand out, and make an impact!
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United States
Consumer Electronics
Functional Verification, Methodology, RTL Design, Test Planning, Debugging, Verilog, SystemVerilog, UVM, C (Programming Language), Python (Programming Language), Big Data Analytics, Digital Logic, Computer Architecture, Verdi, Machine Learning, Embedded Systems, Web Development
Experience
ASIC Design Verification Engineer, Machine Learning
Sunnyvale, CA
Performed unit-level verification of TPU SparseCore blocks using targeted regression testing to debug and validate ML accelerator functionality.
Independent Study - Advanced CPU Design Verification
Penn Engineering
Philadelphia, PA
Conducted independent study on CPU design verification, building reusable SystemVerilog/UVM verification IP and test plans to validate single-cycle, pipelined, and superscalar processor microarchitectures.
Data Research Assistant
The Wharton School
Philadelphia, PA
Conducted data extraction and analysis at The Wharton School using Python-based tools (APIs, Pandas, SQL, network analysis) to study open-source collaboration and build interactive visualizations.
VLSI Digital Read Channel Design and Verification Engineering Intern
Seagate Technology
Longmont, CO
Developed scalable SystemVerilog/UVM verification components in a UNIX environment using Synopsys VCS/Verdi, collaborating on AXI VIP development and identifying RTL bugs in concurrent DRAM transactions.
Undergraduate Research Assistant
NIST University
Brahmapur
Designed and prototyped ASICs for deep learning (BbNN/SNN) in Verilog using FPGA/EDA tools, focusing on neuromorphic optimization and verification workflows.
Teaching Assistant - Python
Internshala
Gurugram
Mentored students in a Python programming course by supporting assignments, debugging, and project evaluation while strengthening hands-on skills in Python, SQL, and GUI development.
ASIC Verification Intern
Scaledge Technology
Bhubaneswar, Odisha, India
- Designed digital circuit, Trained in & built testbench environments for digital & FSM circuits (e.g., sequence detectors) using SystemVerilog.
Education
University of Pennsylvania
Electrical and Electronics Engineering
NIST University
Electrical, Electronics and Communications Engineering
Soumya Dash's Contact Information
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