Snehil Verma

Affiliated with Apple Neural Engine's Compiler Team. • Architected/developed the compiler for ANE to enable DL applications (including Vision Transformers and LLMs) on Apple products with an emphasis on performance and power. • Brought up new hardware silicon and added support for new hardware features in the compiler. • Collaborated with Firmware, Driver, and Platform Architecture teams to achieve the functional and performance goals of various hardware blocks. Also, worked on the definition of new hardware features with the Platform Architecture team. • Contributed to the auxiliary software stack and tooling to support testing and debugging of neural networks.

Advised by Prof. Lizy K. John and affiliated with the Laboratory for Computer Architecture (LCA). • FastPath, ISPASS'19: Proposed a new metric for benchmarking ML workloads from the perspective of comparing training hardware. • NVIDIA GTC'19: An extensive study on the impact of hardware infrastructure choices on deep learning performance for training. • arXiv e-print: Analyzed and characterized the MLPerf [v0.5] training benchmark suite exposing various system-level trends.

EE382V - Hardware Architectures for Machine Learning (taught by Prof. Lizy K. John)

Affiliated with Software, ML Strategic Planning, and Workload Characterization team at Samsung SARC, Austin. • Equipped the OpenCL drivers’ team with a tool capable of capturing, tailoring, and replaying the OpenCL API trace. • Utilized Samsung's proprietary OpenCL Layers and coded a generic library to manage the file input/output efficiently. • Performed an in-depth study on AI Benchmarks and compute workloads, identifying their hot-spots.

Affiliated with PPA (Power, Performance, and Area) and Architecture team at Samsung ACL, San Jose. • Executed power/performance flows on SoC emulation platform to identify performance bottlenecks and blocks using high power. • Developed microbenchmarks targeted at specific architectural features, and initiated the research on ML-based power prediction. • Delved into the design exploration of Texture Cache, analyzed its performance, and studied SOTA Texture Compression techniques

Advised by Prof. Eun J. Kim and affiliated with the High Performance Computing Lab (HPCL). • Proposed and modeled Coherence-Aware Reuse Prediction on ZSim that achieved a speedup of 20% over LRU when evaluated on the PARSEC benchmark suite.

• Tutored students having difficulties in Engineering Design and Graphics by conducting institute level remedial classes and doubt-clearing sessions. Personally mentored academically weaker students to cope with their academic load.

• Worked in a 10-memberd strong team of Executives, responsible for publicity and media coverage of the festival • Co-ordinated and negotiated with over 20 companies for festival sponsorship and finalized deals with them

Track: Architecture, Computer Systems, And Embedded Systems (ACSES)

Professional career development

Minor in Computer Systems, Computer Science and Engineering

IIT JEE preparation.