Sneha Raghunath
AMS Verification, Lead Design Engineer @ Cadence
About
Currently contributing as AMS Verification, Lead Design Engineer at Cadence, focusing on the verification of analog mixed-signal blocks such as Soundwire, eUSB2v2 PHY, and die-to-die interconnects for TSMC and Intel advanced nodes. Proficient in creating behavioral models (BMODs) and validating them with a self-level testbench to ensure system performance and reliability. Skilled in TCL, Perl, and Liberty, with experience working across leading technologies.
India
Bengaluru
Semiconductors
Verilog, TCL, Tcl-Tk, Liberty, Characterisation, SV, SystemVerilog, Exelium, Cosim, Very-Large-Scale Integration (VLSI), Perl, Nanotime, Siliconsmart
Experience
AMS Verification, Lead Design Engineer
Cadence
Hyderabad, Telangana, India
Verifying analog mixed-signal blocks of Soundwire, eusb2v2 PHY die-to-die interconnects for TSMC and Intel advanced nodes. Creating behavioral models (BMODs) and validating them with a self-level testbench to ensure performance and reliability.
A&MS Circuit Design Sr Engineer
Synopsys Inc
Bengaluru, Karnataka, India
A&MS Circuit Design Engineer I
Synopsys Inc
Bangalore Urban, Karnataka, India
Worked on Characterization and STA of A&MS macros using NanoTime & SiliconSmart tool Worked on NLDM, LVF .lib generation for PVTs. Nodes: 3nm, 5nm, 7nm
Engineering Contractor
Synopsys Inc
Noida, Uttar Pradesh, India
Worked with the team of application engineers on Clock Domain Crossing (CDC) analysis and Static Time Analysis. Tools used: SpyGlass and VC Static. Assisted in creating test-benches for URT. Also handled regression test cases.
Trainee
PinE Training Academy of VLSI & Embedded
Ghaziabad, Uttar Pradesh, India
Trained in ASIC Verification.
Education
Raj Kumar Goel Institute of Technology, Ghaziabad
Electronics and Communications Engineering
St Joseph's Academy
Sneha Raghunath's Contact Information
Phone
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