skip coombe

As second employee of a startup founded to commercialize ferroelectric IP established a design environment consisting of hardware, software, and procedures to rapidly translate proprietary memory technology into RfID products characterized by abstract modeling, scripting, continuous improvement, regression testing, and proactive anticipation of problems.

Developed and deployed state of the art mixed-signal design flows to all of Rambus’ world wide design teams with primary responsibility to support the design flow, tools support and automation needs of the local office of 30 designers. Set up design project environments including project structure, revision control, Cadence Virtuoso environment (Schematic capture, layout design, and simulation environment), Standard Cell Library, DRC, LVS, parasitic extraction flows, Synthesis, auto place and route, static and dynamic timing verification flows in a mixed-signal design project.

Leveraged internal Cadence resources to guarantee customer life-cycle satisfaction as primary technical focus for enterprise account. Created tools and worked with in-house engineers to migrate to a license-based CAD environment that resulted in reduced support costs and uniform version management Rescued Cadence software from competitive replacement by creating a cross-functional team that demonstrated superior Cadence accuracy while moving customer’s design to forward

* Senior Member of Technical Staff providing design and methodology leadership. * Responsible for overall design methodology and release criteria for the engine control IC used on all Ford cars and trucks and credited with $175M cost savings * Individual responsibility for design, verification, and testing of microprogram control unit. Invented unique DFT elements that extended fault grading from 98.0% to 99.8% * Team leader for DSP audio IC. Coordinated 3 geographically separated design teams (totaling 30 designers in two companies) that met scheduled milestones over an eight quarter project duration * Individually developed a firmware assembler for VLIW DSP sub-section enabling rapid design iteration during time critical tape-out phase

* Experience in all aspects of digital integrated circuit design * Specification * Abstract and behavioral modeling (Verilog, VHDL, C++, SystemC) * Verification (Verilog, VHDL, Transaction Analysis, Assertion Based Verification) * Physical design and chip finishing * Documentation