Siyuan Chen
Hardware Architecture Modeling Engineer @ Google
About
• Industry and research experience in AI hardware accelerator design, incl. model hardware-software co-design, architectural workload analysis/modeling, and hardware implementation • Computer architect and VLSI engineer with multiple AI accelerator and SoC tape-out experiences
United States
San Francisco Bay Area
Computer Hardware
-
Experience
Hardware Architecture Modeling Engineer
Sunnyvale, California, United States
TPU Architecture
Platform Architecture Intern
Apple
Cupertino, California, United States
Apple Neural Engine
Platform Architecture Intern
Apple
Cupertino, California, United States
Apple Neural Engine
Undergraduate Research Intern
IBM
Yorktown Heights, New York, United States
Worked on hardware security. Supervised by Dr. Gi-Joon Nam.
Education
Carnegie Mellon University
Electrical and Computer Engineering
Advised by Prof. Ken Mai. Worked on machine learning hardware accelerators and VLSI design
Carnegie Mellon University
Electrical and Computer Engineering
Duke University
Electrical & Computer Engineering / Computer Science
Advised by Prof. Krishnendu Chakrabarty
Siyuan Chen's Contact Information
Phone
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