SIMIN JIANG

Get Verilog and SDC from designer , initial the design in ICC,ICC2 or Innovus , floorplan the flat or hierarchical chip level design , including place hard macros , power planning . Define the partitions in deferent power wraps and do trail placement and route for chip level design, commit the partitions, Do timing budgeting for the chip level design. Do top or block level implementation from placement, CTS, routing to timing closure. Generate the SPEF for PT Setup the PT and Tweaker environment for both block and full chip level STA. Deliver the ECO netlist , DEF and Incremental UPF for both Block and top level. Fix the timing manually using Tweaker flow Fix all the PV including LVS DRC ERC ESD for Blocks and Top

Get Verilog and SDC from designer , initial the design in ICC,ICC2 or Innovus , floorplan the flat or hierarchical chip level design , including place hard macros , power planning . Define the partitions in deferent power wraps and do trail placement and route for chip level design, commit the partitions, Do timing budgeting for the chip level design. Do top or block level implementation from placement, CTS, routing to timing closure. Generate the SPEF for PT Setup the PT and Tweaker environment for both block and full chip level STA. Deliver the ECO netlist , DEF and Incremental UPF for both Block and top level. Fix the timing manually using Tweaker flow Fix all the PV including LVS DRC ERC ESD for Blocks and Top

Mercury DCU and L3Cache backend design Floorplanning the design named DL3 and doing partition to apart it to TOP DCU and L3Cache according to the netlist data flow. Doing physical synthesize with module of 2000*7000um.using Alchip fishbone to improve clock skew to get 2GHz frequency.

L2 Cache Memory backend design Do simulation of critical timing path of it using HSPICE and optimize its logic to get the speed of 1Ghz. SRAM sense amplify(SA) design To getting higher speed of SRAM, sense amplify must be designed more aggressively .So the SRAM of 1K(128*8)bits can be read by SA When bit cell`s Q and Qn having a D-value of 150mv. Do simulation of SRAM and customer layout of it. Memory BIST and FUSE backend design Writing SDC , Using Design Compiler to convert Verilog to netlist of MBIST and FUSE. Doing Formal verification. Floorplanning the design. According IR drop planning power mesh, assigning pins to meet 1Ghz timing. Using Encounter to place and route design and Alchip Fishbone flow to decrease clock skew and get better clock structure. Using PT to report timing and writing scripts (such as replace HVT cells with LVT cells) to resolve timing problem. Writing script to make stand cells placed one after another row at vertical orientation and apart from the steps at horizontal orientation. Register File (RF) backend design Customize Domino logic to get higher speed decoder of RF. And all other backend design flows are like L2 Cache . Function verification of Cache and RF are different from other modules due to the difficulty of mapping logical address to physical address. So the vector verification is used. Debugging the wave form using NCSIM finding writing and reading fault. PLL PFD backend design

part time

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