Shubhankar Pawade
Member of Technical Staff @ AMD
About
Completed Masters of Electrical and Computer Engineering at Carnegie Mellon University and joined Intel Corporation. I am interested in the domains of Computer Architecture, Embedded System Design and VLSI Design. In my Masters, I have been involved in projects like Design and Implementation of various Branch Predictors, writing parallel programs using CUDA for K-means clustering algorithm and AES encryption, Complete SoC Design, Developing real-time kernel capable of admission control, task scheduling and synchronization and writing fault collapser for ATPG systems. I believe these projects have immensely aided my learning curve and have given me strong insights in the field of Electrical and Computer Engineering. I have completed my Bachelors of Engineering in Electronics and Instrumentation from Birla Institute of Technology and Science-Pilani, K. K Birla Goa Campus. I have interned at NVIDIA-Bangalore, India for 6 months working in GPU Full-chip Verification Team. Primarily, I collaborated with my team in debugging GPU full-chip bugs using System Verilog test cases. I was also involved in development of audio controller transactor for performance analysis of GPU units, and building reset checker for validation of proper functioning of all reset signals in the system. I have done academic projects spanning various domains like Computer Architecture, Embedded systems, VLSI architecture, Memory Systems, Wireless sensor networks and Digital Signal Processing.
United States
San Jose
Semiconductors
Design Specifications, RTL Verification, Cache Coherency, Functional Verification, Test Planning, System on a Chip (SoC), RTL Design, TCL, Jasper, Formal Verification, Assertions, Very-Large-Scale Integration (VLSI), Verilog, Core Java, Test Cases, Systems Design, Debugging, C, AutoCAD, VHDL
Experience
Member of Technical Staff
AMD
Santa Clara, California, United States
Staff Formal Verification Engineer
Samsung Semiconductor
Formal Verification Engineer
Intel
Hillsboro, Oregon, United States
• Feature Validation - Test planning, formal assertions, covers, constraints, functional coverage and sign-off • Validation of Cache Coherence, Security, Performance and Functional features • Validation Methodology - formal tools and techniques like abstractions, proof accelerators and reductions • Architected overall Formal Validation infrastructure • Tools - experience in JasperGold FPV, Coverage, XPROP Apps, Superlint
Teaching Assistant
Carnegie Mellon University
Greater Pittsburgh Area
Teaching Assistant for ULSI Technology Status and Roadmap for System on Chips and System in Package (18664)
Research Assistant
Carnegie Mellon University
Greater Pittsburgh Area
Worked on developing a software infrastructure to access memory by row-buffer locality to minimize row-buffer misses. The project assumed that the data set is very large and sparsely scattered such that consequent accesses may not be present in last level of cache. Thus, there could be a huge penalty to access the DRAM if there are large number of row-buffer misses. Tried tackling this issue during the Summer'19 and currently working on it for Research Credits.
Intern
NVIDIA
Bangalore
- Aided in development of reset checker for validation of proper functioning of all reset signals in system - Developed an audio-controller transactor for performance analysis of GPU units - Assisted in memory management unit verification by resolving bugs for GPU fullchip using System Verilog test cases
Design Engineering Intern
ECLIPSE INSTRUMENTATION PVT. LTD.
Thane, Maharashtra, India
- Analyzed the design of Electro-surgical units used in medical sectors for its performance analysis - Designed PCB layout for the upcoming Electro-surgical units of the company - Examined the power electronics involved and fail-safe circuitry of the design
Education
Carnegie Mellon University
Electrical and Computer Engineering
Shubhankar Pawade's Contact Information
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