Shruti Sinha

With over 21 years of experience in the VLSI industry, I specialize in FPGA and ASIC design, leveraging expertise in Python, RTL design, and SystemVerilog. My current role as Senior Staff Manager at Marvell Technology focuses on delivering high-quality RTL subsystems for Datacentre chips alongside global teams. At Marvell Technology, I contribute to technical leadership, project management, and team collaboration, ensuring seamless RTL design implementation and integration. I am passionate about empowering teams to achieve excellence in IP design through innovation and execution and a strong believer and executer of AI tools and technologies. A Gold Medalist and University Topper from Pune University, I hold International patents and certification as a Data Scientist. My technical acumen is matched by commitment to mentorship and inclusion , serving as a core member of WiSE(Women in Semiconductor & Electronics), community under IESA. Your organization's data cannot be pasted here.