Shruthi Kondajji Halagappa

Hardware Engineer @ Qualcomm

About

Graduate in Electrical Engineering master’s at Arizona state university with a strong technical background in Digital Systems and Circuits, VLSI ASIC design, Physical Design, RTL design. Skills: • Tools: EDA Tools - Cadence Virtuoso, IC Compiler, Innovus, Spectre, Mentor Graphics Calibre, Modelsim, Synopsys Design Compiler, Fusion Compiler, Verdi, H-Spice, PrimeTime PX, Waveviewer, Matlab- Simulink, Gem5, ANSYS • Programming: Verilog, Python, Tcl. • Operating Systems: Linux, Windows. • Core skills: Physical Design, Static Timing Analysis, Power Performance Area Analysis, RTL Coding using Synthesizable constructs of Verilog, Synthesis, FSM based design, Logic Verification, ASIC Design, Code Coverage, Functional Coverage.

Country

United States

City

San Diego

Industry

Consumer Electronics

Skill

PPA, Circuit Design, ICC II, Static Timing Analysis, Floorplanning, Cadence Innovus, SystemVerilog, RTL Design, Colab, Machine Learning, Convolutional Neural Networks (CNN), Innovus, Fusion Compiler, ASIC , Physical Design, TCL, Synopsis Design Compiler, DFT, Digital IC Verification, Digital IC Design

Experience

Hardware Engineer

Qualcomm

2025-5 - Present · 1 yr 4 mos

San Diego, California, United States

Working in Qualcomm’s core DTCO team, focusing on block-level synthesis to physical design (PD) for PPA (Power, Performance, Area) analysis and regression to evaluate DTCO booster impacts. Responsible for interpreting complex PPA data, driving optimization strategies, and contributing to design enablement across advanced nodes. Collaborate closely with cross-functional teams and external partners including foundries, EDA vendors, and research institutions to advance physical design methodologies and DTCO innovations.