Shrikant S.

Design Verification Engineer @ Annapurna Labs

About

I lead hardware verification for DMA engines at the chip level, ensuring silicon works before tape-out. My work spans UVM testbench development, debugging across simulation/emulation, coverage closure, and driving designs to readiness.I focus on building systems that make teams faster — not just fixing individual bugs.What I do:• End-to-end verification of high-performance DMA (queues, memory transfers, reorder buffers, interrupts, error handling)• Own verification plans, UVM environments, regressions, and deep debug — consistently delivering milestone coverage targets on schedule• Partner cross-functionally to prioritize real risk over superficial coverage gaps, catching integration defects months earlier than sequential validationTeam & impact:• Defined hiring standards and interview frameworks — shaped a team that operates with less senior oversight each quarter• Mentor engineers in structured debugging and root-cause thinking — multiple mentees now lead independent verification effortsAI/LLM work:• Built 10+ structured AI frameworks enabling LLMs to perform real verification tasks (triage, root cause, code checks, bring-up)• Developed failure pattern libraries (50+ signatures), regression workflows, and agent guardrails used daily by the team• Cut regression triage time by ~60% and reduced average root-cause cycles from days to hours through AI-assisted workflowsOther contributions:• Led VIP vendor evaluation — drove data-backed procurement decisions saving weeks of integration effort• Built cross-stage validation frameworks (simulation → emulation → post-silicon) that eliminated a class of infrastructure escapes previously invisible to pass/fail metricsWhat drives me:Build systems, grow people, and scale impact across teams.

Country

United States

City

Cupertino

Industry

Computer Software

Skill

Anthropic Claude, Amazon Q, Ucie, Hardware Engineering, Hardware Development, Quality of Service (QoS), RISC-V, Interrupts, Microsoft Azure, Interconnects, Hardware Architecture, XML, Synopsys tools, YAML, RTL Design, System on a Chip (SoC), Data Analysis, Data Visualization, Code Coverage, sva

Experience

Design Verification Engineer

Annapurna Labs

2024-10 - Present · 2 yrs

https://aws.amazon.com/ai/machine-learning/trainium/

Staff Hardware Engineer

Tesla

2023-2 - 2024-10 · 1 yr 9 mos

Palo Alto, California, United States

DOJO project: Lead Verification effort for Tesla’s Custom RDMA protocol over Ethernet (TTPoE), TTPoE distributed congestion management in hardware . Scale up over Clos network. Descriptor workload over RDMA and TCP/IP verification . https://github.com/teslamotors/ttpoe

Senior Design Verification Engineer

Microsoft

2020-1 - 2023-2 · 3 yrs 2 mos

MAIA100: Responsible for Design Verification for High Bandwidth Interconnects, SoC Test plan development,Fabric IP Functional Verification, Performance Verification and Benchmarking, Support multi-chip stress testing and bringup for post-silicon validation. Cross functional collaboration with Architecture, firmware and Design Teams. Risk mitigated performance bottleneck in architecture via architecture modelling and simulating real workloads in pre- silicon environments .

Member of Technical Staff

Fungible, Inc.

2019-7 - 2020-1 · 7 mos

Santa Clara, California, United States

Network subsystem IP level verification using UVM

Developer

OURS Technology Inc

2017-3 - 2019-6 · 2 yrs 4 mos

One of key engineers in silicon valley startup, contributed on Test bench orchestration and automation for various componenets. L2 cache up verification for riscV based inference SoC

Lead Design Verification Engineer

Cavium Inc(Acquisition)

2013-10 - 2017-3 · 3 yrs 6 mos

I contributed to the Data-Center Silicon Network Switch program as Design Verification Engineer. I was responsible for Traffic Manager and Packer Header Processor Verification for 1st Gen reticle size project. Support Validation for bringup and Customer Support Teams for triage.

Design Verification Engineer

XPliant

2013-3 - 2013-10 · 8 mos

Joined startup thst was acquired by Cavium. Joined as design verification engineer and was promoted 3 times to lead engineer in 3 years.

Design Verification Staff

Broadcom

2010-10 - 2013-3 · 2 yrs 6 mos

San Jose, California, United States

Trident 2 & Tomohawk : As a recent College Graduate I was responsible for scaling up pre existing tests for Built-In-Self-Test memory verification for the Ethernet Network Switch Team. My career growth lead me to be responsible for Packet Policing and QoS units in Tomahawk and Trident class industry leading Network switches.