SHRIHARI RR

Staff Design Verification Engineer @ Samsung Electronics

About

Graphics hardware engineer with 10+ years of experience in successfully delivering high performance graphics solutions on pc, server and mobile platforms. SKILLS: • Object Oriented Programming in JAVA and System Verilog • Experience owning and maintaining UVM testbench • Full verification ownership of IPs • Scoreboard development and ownership • Constrained random testing in System Verilog LANGUAGES: JAVA, System Verilog, Perl, Python, C, C++. TOOLS and framework: UVM, IntelliJ, Eclipse, Verdi, Synopsys DVE, Cadence Virtuoso, RTL compiler, ModelSim, NC-Verilog, Active HDL, Design Compiler, Synplify Pro, Xilinx ISE, GemV.

Country

City

United States

Industry

Semiconductors

Skill

Graphics Processing Unit, Code Coverage, DV, Logic Gates, Programming Concepts, Low-power Design, Digital Designs, Communication, Technical Documentation, Hardware Engineering, Computer Engineering, Simulations, Coverage Analysis, Perforce, Electrical Engineering, Computer Science, Analytical Skills, Object-oriented Languages, Hardware Description Language, Problem Solving

Experience

Staff Design Verification Engineer

Samsung Electronics

2023-4 - Present · 3 yrs 5 mos

Graphics Hardware Engineer

Intel

2015-4 - 2023-4 · 8 yrs 1 mo

Research Assistant

Arizona State University

2012-9 - 2015-3 · 2 yrs 7 mos

Tempe

Complete Ownership of ASIC flow for Coarse Grained Reconfigurable Array (CGRA) Processors • Designed CGRA chip from specification to layout generation (RTL to GDSII). • Performed RTL Design (Verilog), Verification, Synthesis, Equivalence Checking, Static Timing Analysis & Auto Place and Route of the CGRA chip. Novel Compiler for CGRAs •Invented and implemented a novel LLVM compiler technique for efficient execution of control flow in CGRA accelerator chip. •Achieved 34.6% performance improvement via speedup. •Achieved 52.1% improvement in energy efficiency over state of the art solution.

Graduate Teaching Assistant

Arizona State University

2012-7 - 2013-6 · 1 yr

Tempe

Taught and supervised lab projects for VLSI Design and Analog and Digital Circuits courses involving: • Design of Analog and digital circuits in CMOS using CADENCE design suite • Circuit simulations using HSpice and Spectre • Generation of Layouts for custom circuits • Calibre's DRC and LVS check and Parasitic extraction using QRC