Shravan Padala

1. Currently working at Intel as a SoC Design Engineer with 5+years of experience in ASIC Physical Design. 2. Skilled in working on advanced technology nodes such as 5nm,7nm, 10nm, and 14nm. 3. Proficient in block-level implementation from Synthesis to GDSII. 4. Strong expertise in Static Timing Analysis (STA), Synthesis, Floor planning, Placement & Routing, and Clock Tree Synthesis (CTS). 5. Hands-on experience in timing violation fixing, ensuring minimal DRC impact even in highly congested designs. 6. Well-versed with industry-standard physical design flows, verification methodologies, and EDA tools. 7. Proficient in using tools such as Primetime (PT), Fusion Compiler (FC), ICC2, Design Compiler (DC), and Conformal. 8. Recognized for excellent work ethic, analytical mindset, and strong problem-solving and troubleshooting skills.