Shih-Chieh Lin

Senior Design Verification Engineer @ NVIDIA

Country

Taiwan

City

Hsinchu City

Industry

Semiconductors

Skill

Universal Verification Methodology (UVM), SystemVerilog, C, C++, Digital Image Processing, Chinese to English, English to Chinese, English Translation, Image Segmentation, Machine Learning

Experience

Senior Design Verification Engineer

NVIDIA

2024-1 - Present · 2 yrs 9 mos

Hsinchu City, Taiwan, Taiwan

PCIE Controller IP verification

Senior Design Verification Engineer

MediaTek

2021-6 - 2024-1 · 2 yrs 8 mos

Hsinchu City, Taiwan, Taiwan

--Design verification for 5G smartphone SoC bus. (task level, moving on to subsys level) --Design verification for in-house small-scale IP (Dynamic Voltage/Frequency Scaling Resource Collector) --Learn about design verification flow, including Spec/standard reading (AMBA AXI/AHB/APB, in-house bus spec), test plan writing and System Verilog implementation. --Discuss and cooperate with designers to improve test plans for expected coverage.

Design Verification Engineer

Realtek Semiconductor Corp.

2020-8 - 2021-5 · 10 mos

Hsinchu City, Taiwan, Taiwan

-- Design verification for Ethernet switch IC (Automobile). -- Learn about design verification flow, including spec/standard reading, test plan writing and System Verilog implementation. -- Learn about new verification tools and concepts, including UVM, Certitude…etc -- Discuss and cooperate with system/IC designers to improve test plans for expected coverage.