Shalini Gupta

• Working on 7nm Physical Design project, includes Floorplan, power planning, CTS , PnR, STA, Physical verification. • Managing the Physical Design team at client location • Technical Consultant for Synthesis, PnR and Timing Closure across multiple clients • Understanding the technical specifications and complexity to create Physical Design Proposals • To Provide In-House training for team in Synthesis, STA and PnR • PD-recruitment and team building

● Lead consultant for team working on 14nm physical design project. ● Ownership of 34 blocks with varying complexity in technical execution. ● Floorplan, powerplan, CTS, place and Route, STA, constraints ownership. ● Ownership of feasibility analysis at top level with different floorplans. ● Analysis of feasibility of RTL changes from PD perspective for my partition and for others. ● Successfully done synthesis optimisation, placement and routing for partition and released timing clean and ICC DRC clean database. ● ECO rollups (functional/non-functional) ● Managing team of 25 members.

● Constraints Development at Full chip level. ● Synthesis and optimization, Physical Synthesis, Power Design, Formal Verification, Timing Closure with Crosstalk and OCV in all modes and corners. ● Interaction with Physical Design team, Signoff for power design checks and HLDRC checks. ● Managed Client interactions and team. ● Porting of SoC RTL to Zebu boards for multiple SOC. ● RTL modifications for FPGA, synthesis, and place and route, device specific verification support, debugging connectivity with JTAG interface, area and stability issues due to multiple FPGAs (it is 3 FPGA – Vertex4 at the time) ● Prototyping new features on FPGA for future design and silicon validation support for failed scenarios by replicating them on FPGA. ● Integration of IPs to create full SOC, RTL code for interfaces and additional logics. ● RTL and Gate level simulations, and validation suite implementation ● Module synthesis and device level net list generation. ● Formal verification RTL-Netlist, Netlist-Netlist, ● Constraints creation and STA for all modes (functioan/test)

● Support for design of MPEG encoder-decoder interface and MPEG decoder-RCA jack interface.