Sanket Patel
Interim Engineering Intern @ Qualcomm
About
• 1-year research experience: Conducted research and simulation of solar thermal energy absorbers using COMSOL, MATLAB, and Python.• Published in 3 Q1 top-tier international SCI-index journals• 6-month ASIC & FPGA internship: Gained practical experience in digital design using Verilog, GPU fundamentals, and verification with SystemVerilog.• Coursework: In-depth academic training in DRAM, cache hierarchy, interconnects (Portland State), ASIC modeling, synthesis, pre-silicon validation using SystemVerilog and the UVM framework, and formal verification methods including Binary Decision Diagrams (BDD).• Looking for internship/co-op in ASIC Design starting September 2026 and full-time position starting December 2026.• Contact: sanketp@pdx.edu
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United States
Computer Hardware
CPU Architecture , Test cases and Test Plans Development , Object-Oriented Programming (OOP), Microarchitecture, CDC, Lint, RTL Coding, RTL Design, Computer Architecture, MIPS, Git, Logic Design, Digital Electronics, SystemVerilog, Communication, Engineering, Design, Hardware Design, Digital Designs, Digital Logic
Experience
Interim Engineering Intern
Qualcomm
San Diego, CA
Incoming Summer 2026 - Qualcomm
Graduate Student
Portland State University
Portland, Oregon, United States
ASIC Verification Intern
Indeeksha Digital Pvt. Ltd
Ahmedabad
Junior Research Fellow
Marwadi University
Rajkot, Gujarat, India
~Research concentrated in the area of photonics consists of Solar Energy Absorber (green-energy applications) [Patel Photonics and Metamaterials Research Group]
Undergraduate Research Assistant
Institute For Plasma Research
Gandhinagar, Gujarat, India
~Proficient in utilizing software tools such as NI LabVIEW and NI MAX for configuring PXIe-1082 cards, ensuring seamless integration and operation. ~Played a vital role in a 2-member team working on the LIGO project, contributing to research, software development, and hardware compatibility testing for GPS-based timing signal generation and time synchronization. ~Successfully designed and implemented a synchronization system achieving a remarkable accuracy of 10ns between the PXIe device and the signal source, ensuring precise coordination and synchronization in the setup.
Digital Design Intern
eInfochips (An Arrow Company)
Education
Portland State University
Electrical and Computer Engineering (Design, Verification & Computer Architecture Specialization)
Coursework: Fall’24 ECE 581- ASIC Modelling and Synthesis ECE 585- Microprocessor System Design ECE 508- SystemVerilog Workshop Winter’25 ECE 582- Formal Methods ECE 593 - Pre-silicon Validation ECE 508- Computational Tools Workshop Spring'25 ECE 581 - Introduction to SystemVerilog ECE 586 - Computer Architecture Fall'25 ECE 587 - Advanced Computer Architecture I ETM 508 - Technology Evaluation using Artificial Intelligence Workshop Winter'26 ECE 588 - Spring'26 ECE 530 - Physical Design of Digital Integrated Circuits ECE 510 - Post- Silicon Functional Validation ECE 508 - Python and Scripting Workshop Fall'26 ECE 560 - Assertion Based Verification (ABV)
Dharmsinh Desai University
Electrical, Electronics and Communications Engineering
State Government Scholarship Recipient (Four Years) ONGC Scholar (Throughout Undergraduate Program)
Sanket Patel's Contact Information
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