Sang Trinh

(Staff Design Verification Engineer) From 2nd/Jun/2025 till present: MCU Automotive Microcontroller Development, Chip Development, Chip Verification, Infrastructure & System team. - Working on SoC MCU Chip Verification related to Security cluster block functions. (Staff Digital Design/Design Verification Engineer) From Nov/2022 to 30/May/2025: Design Engineer Services, Design Operation Services, Analog Mixed Signal, Design Sub System team. -Familiar with (Infineon + Cypress) HOBTO IP development flow. -Created RTL code (Verilog/System Verilog) for Timer - HRPWM IP (updating function for High Resolution PWM) -Confirmed Lint/Spyglass + Spyglass-CDC (Clock Domain Crossing) check to confirm quality of design with all syntax and all design rules. -Made Synthesis using Cadence/Genus, DFT scan insertion, UPF insertion. -Logic Equivalent check (LEC) RTL <> Gate netlist, Pre-DFT netlist <> Post-DFT netlist, -Made STA (Static Timing Analysis) using Cadence/Tempus. -Make RTL Power Analysis (Primetime) realize and estimate total power leakage (Static/Dynamic power) -Made testcase (System Verilog) for simulation functional verification using Questa Sim in UVM env testbench. -Made quality released with IP design final released (AIP) Accept IP check. -Created RTL code (Verilog/System Verilog) for some modules DCSG_IF, DCSG threshold correction, Min/Max detection, CIC filter of ATOPSS (Analog/Digital sub-system) -Doing Functional Digital Verification for DCSG module (connecting DCSG ANA block and DAC- Digital Analog Convert) and creating testcase (System Verilog) using UVM env with Questa Sim. -Made test patterns for ATOPSS Test Vector Development released to Testers for doing wafer test.

- I worked for full design flow from Specification/Design/Verification/Timing design, .. etc (also all Frontend Design development) for MEM/Flash and Security modules (U2A-EVA/U2A6/U2B_FCC/U2B6/U2B10, U2C8/U2C4) projects (28nm chip) for for MCU Chips (Unicon, Cross domain, UniMIND). + Checked and confirmed Customer requests (RFQ) to make Requirement specification. + Made Hardware User Manual specification to released SW development and also released to customers. + Created Functional specification/Block diagram for logic design development. + Deep understanding design flow and STARC RTL Design Style Guide Verilog-HDL. + Understanding & knowledge with Functional Safety (ISO26262), Security (ISO23414). + Deep understanding DFMEA (Design Failure Mode Effect Analysis)/DRBFM (Design Review Base on Failure Mode) + Experienced on Technology Verification methodology: -VCS compile check -Spyglass check -DFT check -HLDRC check -STA check (Asynchronous transfer) -UPF and power related function specification design. -Do synthesis & making report, timing report, Design Compiler report, Fusion Compiler. -Equivalence checking, Logic Equivalent Checking (LEC), Formality (FV)/Conformal LEC. -Experience on Functional verification using Verilog verification environment (UVM, MCU Renesas in house tool with MUVE env, RECcheck, ...etc) -Experience and Knowledge of CPU (especially RH850 families) and Flat form Sub system (PFSS) include SRAM/FLASH, Interrupt, DMAC/DTS. ECM (Error Control Modules), ... etc -Experience and Knowledge of SRAM hard macro, VMC, FLASH SM/HM, ... etc -Experience Functional Verification using Assembler (*.asm) and C code (*.s/*.c) and System verilog, SVA (System Verilog Assertion). -Experience Formal Verification Static Check (IFV/Jasper Gold, VC Formal) -Experience and Knowledge with STA Timing design (Static Timing Analysis) and Special Timing (Kobetsu), AC timing.

- I worked on Design/Verification for MEM/Flash and Security modules (E2H) projects (28nm chip) for MCU Chips (Power train, Chasis & Safety)

- I worked 1 year at Renesas at Kodaira, Tokyo, Japan (Musashi - REL) which as design center of head quarter in Renesas Tokyo (Japan). - I worked on Functional Design and Functional Verification for MCU Chips (Power train, Chassis & Safety) in MEM/Flash and Security modules (Renesas: Intelligent Cryptographic Unit (ICU)) in (E2x_FCC2/E2UH) projects (28nm chip) which Global One team with Japan outsource team and Japanese partners/China/Viet Nam partners (both of Product team & IP team, System design team, DOC User team, Middle End/Back End team. • Design/Verify for MEM_TOP (Security ICUM/Flash FPSYS) and all related front end development tasks. (Notes) Renesas/E2x_FCC2 is the World’s First On-Chip Flash Memory Microcontroller Featuring Advanced 28nm Embedded Flash Technology (since March 27, 2018)

- I worked Design/Verification for MCU Chips (Power train, Chassis & Safety) in PFSS block (Flat form sub system), Peripheral block modules (E1x_FCC2/E2M/E2x_FCC1) projects (40nm chip) • Design/Verification (Combine test) for Peripheral blocks (P-Bus guard, ECC, Module standby, RSENT, ...etc) • Design/Verification (Unit test) for PFSS IP (Bus, Flash, INT, DMA, ..etc), (Combine test) for PFSS_TOP block (PBus access, HBUS Master/Slave, SRAM access, ..etc)

- I worked Design/Verification for RH850 Automotive MCUs Chips (Power train, Chassis & Safety) in Peripheral modules (PFC1B, E1x_FCC1/E1MS2/C1MA PFSS Plat form sub system, P1ME) projects (40nm chip) • Design/Verification P-Bus guard, ECC of Peripheral blocks (RSENT, CSIH, RLINK, SCI,...) • Build up PFSS IP (Flat form sub system) connect with (CPU, Bus, INT, Flash, ..etc) • Synthesis and gate netlist checkers (DFT/HLDRC/STAcheck/Amataras) confirmation for Port design (Port function, Level shifter, IO) - Created and confirmed Virtual Tester verification simulation env in E1MS2/RSENT module and exported Extended Value Change Dump (EVCD) and Standard Test Interface Language (STIL) for tester machine/automatic test equipment (ATE) in tester phase.

- I worked Nhat Bao Tin company for setting up Machine equipment (Valves system, coffee drying system, Automation sensor/mechanic,... etc at Netle Tri An factory, Amata Industrial park, Bien Hoa district, Dong Nai province, Vietnam. - I had communicated and cooperated with their experts from Netherland & Germany for setting up these machine/automation technologies systems (as valves, coffee dry, temperatures, ...) which imported to building up in the factory.

- Assisted technician engineers to repair electronic devices in automation control systems in the factory at Long An provinces, Vietnam. - Practiced design automation control valve systems projects using Phoenix Contact PLC.

- Project 1: Excellence designed (Proteus/OrCad PCB) of MCU chip PIC16F877A in CCS to perform real circuit operation of Traffic lights display with real time into led 7 segments in crossroads. - Project 2: Excellence designed (Proteus/OrCad PCB) of MCU chip PIC16F877A in CCS to perform real circuit operation in display communication monitor (many display mode) in LCD. - Project 3: Excellence designed (Proteus/OrCad PCB) of MCU chip PIC16F877A in CCS to perform real circuit operation of temperature control system by using sensor LM35, DC motor, ... also display analog temperature in real time to led 7 segments. - Thesis graduation: Excellence designed real circuit with Programmable-Logic-Controller (PLC) of operation of PUMPING station (with AC motor) factory with both of Dashboard HMI interface (via C#) to directly control, remote control AC Motor using mobile phone to sending message command in Global System for Mobile Communications (GSM) to PLC which connect MCU chip PIC16F877A.