Sandip Sadadiya

• Over 15 years of strong experience working across the complete AMBA family of VIPs, with exposure to top-tier sem-iconductor companies. • Extensive industry experiences spanning IP, SoC, ASIC, FPGA, Test Chip, and VIP verification and validation. • Onsite experience at customer locations including AMD (Shanghai) and Ericsson (Sweden). • Proven leadership in managing IP/SoC verification teams and direct client interactions. • Skilled in building and mentoring teams for IP/SoC verification projects. • Hands-on experience in VIP development and verification using SystemVerilog and UVM methodologies. • Proficient in Assertion-Based Verification using SystemVerilog. • Strong knowledge of Code Coverage, Functional Coverage, Formal Verification, and Gate-level Simulation. • Technical expertise in SystemVerilog, UVM, Verilog, VHDL, FPGA, C/C++, TCL, and Perl scripting. • Experienced in protocol-based design and SoC verification using Verilog and SystemVerilog. • Solid background in developing and supporting SoC and module-level test benches. • Skilled in test bench support and regression management. • Direct customer engagement experience, from requirement gathering to delivering complete verification solutions. • Proficient in managing test configuration files for VTC regression environments. • Experienced in developing test plans, designing verification components, and driving coverage closure for complex designs. Technical Skills: • Programming Language : Verilog, System Verilog, VHDL,C, C++ • Scripting language : TCL, Perl, Python • Methodologies knowledge : UVM • Protocol Knowledge : AXI3/4/5, Lite, Stream, APB, AHB, Fiber Channel VIP/ Ethernet ,Nand Flash Controller, I2C, I3C, SPI, UART, EHP, Bootrom • Technologies : Ether CAT, GSM & CDMA, 5G • EDA Tools : Questasim, VCS, XILINX, 12.3, keil micro vision in • Operating Systems : Windows, Linux.