Szu-Han Chen
Student Researcher @ University of Southern California
United States
Los Angeles
Consumer Electronics
Phase-Locked Loop (PLL), Electro-Mechanical Design, RF Circuits, Finite Element Analysis (FEA), Programming Languages, Phase Noise, Oscillators, SPICE, Research Skills, CAD Tools, Cadence Virtuoso, Ansys Mechanical APDL, COMSOL, Autodesk Inventor, AutoCAD, Project Management, Analog Circuit Design, Mixed-Signal IC Design
Experience
Student Researcher
University of Southern California
1. Transistor-level simulations of Type II PLL in Cadence Virtuoso using TSMC 65nm PDK. 2. Optimizing LC VCO’s phase noise to achieve low-jitter PLL for high-frequency application. 3. Phase noise = -140 dBc/Hz, Power = 8.42 mV, FoM = -189 dB
Research Assistant
Taiwan Semiconductor Manufacturing Co., Ltd
Technical support in building a piezoelectric platform, including chip design and manufacturing parameter testing, to establish material properties data base for TSMC.
Education
USC Viterbi School of Engineering
Integrated Circuit Design
National Tsing Hua University
Semiconductor Manufacturing Technology
Master thesis: Design and Implementation of Piezoelectric MEMS Scanning Mirrors System for Imaging Applications. (Supervisor: Prof. Weileun Fang)
National Tsing Hua University
Mechanical Engineering
Undergraduate senior project: Underactuated system for Spinal Monitoring and Posture Correction (First place, Dec. 2020)
Szu-Han Chen's Contact Information
Phone
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