Sameera Talari

- Contributed to the microarchitecture development and RTL-to-GDSII handoff of PCIe Gen5/Gen6 IP (Blackwell/Rubin project), coordinating with architecture, verification, physical design, and neighboring IP teams across multiple high-performance SoCs. - Owned end-to-end design of the Transmit datapath for PCIe Data Link Layer, collaborating with Physical Design to achieve timing closure at 1 GHz and meet PPA targets through optimized timing/area trade-offs; partnered with verification teams to resolve corner-case issues, achieving 95% functional coverage. - Resolved critical pre-silicon RTL bugs via ECO using Mender/Vivid tools, validating RTL–netlist equivalence through detailed netlist analysis to prevent post-silicon re-spins. - Managed IP delivery and chip-level integration by establishing top-level port connections between PCIe IP and interactive modules across cross-functional teams.

- Developed comprehensive microarchitecture and RTL for the PCIe Data Link Layer (Gen3/Gen4/Gen5) across all lane configurations (x1/x2/x4/x8/x16). Designed and architected the PCIe Data Link Layer Replay module, optimizing Retry Buffer utilization for efficient storage and sequential mapping of variable-length TLPs to meet PPA targets. - Debugged PCIe lower-generation legacy IP at RTL and FPGA levels; led cross-functional workshops to develop low-power architecture for power management without compromising performance; achieved timing closure by synthesizing and optimizing Data Link (DL) RTL using Synopsys Design Compiler to meet 1 GHz timing target, verified timing using PrimeTime; performed power estimation using PTPX and implemented strategies to reduce power consumption.

– Worked on Secure USB 3.0 project in association with DRDO, optimised data path of a module for better timing performance. – Cleared VCS and DC lints of design.

Resources efficient hardware DNN accelerator is proposed and implemented on FPGA using Vivado tool using HDL language. A nonlinear activation function is resource hungry for higher precision, during MAC computation AF is in sleep mode but is dissipating static power hence used a single activation function for the whole layer. The same proposed customized hardware is also implemented on ASIC, used ModelSim for simulation, Synopsys DC for synthesis and PrimeTime to check if timing is being met. Now we are looking forward for post-layout implementation in Cadence Encounter to place and route design for the 196-16-10-4 network. Further will be sending chip for tape out.

I worked on project titled "SSR mitigation in wind energy power system" that comes under power system domain. As part of project, I developed a program by understanding mathematical realization of wind energy systems in MATLAB Simulink. This project was aimed to launch a concept based cognitive skills for analysis in Electrical Domain Research.

Internshala Student Partner (ISP 14) is a work-from-college program where they hire students from different colleges across India and teach them essential skills like Public Speaking, Networking, Time Management & Customer Service and my day-to-day responsibility included promote Internshala internships among my peers,helping my peers learn new skills via Internshala Trainings ,train my peers to get an internship.

Relevant Coursework: - Principles in Computer Architecture - Special Topics in Computer Engineering - Low power VLSI Implementation for ML - VLSI Digital System Algorithms and Architectures - VLSI Integration Computing Circuitry

Relevant Coursework : - Digital Circuit Design - Digital Systems - Electronic Devices - MOS Devices & Modeling - Microprocessor and Digital Systems Design - VLSI Systems and Technology