Samarth Bonthala

Building Adreno GPUs - Shader Core RTL Design

RTL Design - SweRV Cores - RISC-V

Verification of Vera CPU Chiplet

1) Test plan development from scratch for clock controller and clock monitoring IPs in Automotive SoCs 2) Hands-on experience in developing test-bench features for a brand new sub-system 3) SV-UVM based IP level verification of clock controllers 4) Fault Campaign to prove ASIL-D compliance for automotive applications 5) Formal Property Verification using VC Formal to prove the behavior of custom-logic within the IPs being verified 6) Developed a new member training site to act as a one-stop reference containing links to training resources organized methodically, FAQs along with solutions, common DV environment issues and pointers to resolve them and weekly status updates 7) Support team members to debug failing test scenarios while verifying complex multi-processor - (ARM/custom), cache coherent SoCs intended for diverse applications 8) Deliver quality vectors for verifying the post-silicon functionality of the chip and ensured sufficient configurability is provided to adjust certain registers without re-generating vectors when a test sequence is required. 9) Delivered the clock tree vector across projects for SoC power estimation and worked closely with the SoC power team and the power validation team to analyze the power numbers and correlate the pre-silicon numbers with those extracted from post-silicon analysis.

1) Responsible for SoC level verification of clock controller IPs for Snapdragon mobile SoCs. 2) Ensured high-quality of functional vectors from clocking perspective, delivered from SoC DV for post-silicon bring-up and other engineering activities 3) Developed a methodology using PERL and SLN to enable clocks in simulations on a use-case basis - achieved improvement in simulation time and uncovered corner case clock dependencies. Additionally, trained team members across sites - Noida, Chennai, and Hyderabad to deploy this efficient methodology in their flows - leading to 20% reduction in simulation times

1) Voluntary position at IEEE Young Professionals Affinity Group Bangalore. 2) Established a mentorship forum, Mentor4You - connected engineering students with mentors from the industry and academia to guide them in choosing the right career path and offer technical support on their projects. 3) Volunteered as the Program Co-Chair of IEEE Region 10 Humanitarian Technology Conference held in Bengaluru in October 2021

1) Led the team to organize quality technical and professional events - seminars, workshops, summits, hackathons, and coding contests for skill development of NITK students and finding value in their membership. 2) Implemented new initiatives to empower freshmen students. Established Envision, a fully-funded project-based learning forum where freshmen worked on projects in their domains of interest, mentored by sophomores and junior-year students. ENVISION was awarded the "Darrel Chong Student Activity Award" by the IEEE. 3) Led a team of 70+ student volunteers from across India on various portfolios such as sponsorship, logistics, finance, outreach, hospitality, and website to successfully organize the maiden edition of the Women in Technology Summit. 4) The student branch was recognized with the "Regional Exemplary Student Branch" award for its activities and contributions during my tenure.

1) Investigated the feasibility of developing a methodology to minimize the time for coverage analysis and closure for derivative projects 2) Developed scripts that report coverage metrics (toggle, functional and code) on the delta ports, registers and lines between multiple baselines of an SoC

1) SPICMACAY stands for Society for Promotion of Indian Classical Music and Culture Amongst Youth. This movement was started by Dr. Kiran Seth, Professor Emeritus, IIT Delhi to promote Indian culture. 2) SPICMACAY NITK Chapter coordinates activities of the organization at NITK and supports Mangalore Chapter to organize classic music and dance concerts in the region. 3) I maintained the books for a period of one academic year (two semesters) and educated my juniors to effectively transition into my role at the end of my tenure.

1) Developed a scalable MATLAB tool to process characterization data of nano-devices fabricated at IISc and extract parameters such as transconductance, sub-threshold slope, hysteresis, and field-effect mobility. 2) Worked on state-of-the-art device characterization equipment to extract data for Molybdenum Sulphide devices and further analyzed the Id-Vd and Id-Vg plots to determine the conformity of extracted parameters with the trends predicted in literature

Specialization: Architecture, Computer Systems and Embedded Systems (ACSES) Courses: 1) Computer Architecture - Prof. Dam Sunwoo 2) VLSI Design - Prof. David Pan 3) Verification of Digital Systems - Prof. Monica Farkash 4) Hardware Architectures for Machine Learning - Prof. Lizy John 5) Advanced Embedded Microcontroller Systems - Prof. Mark McDermott 6) High Speed Computer Arithmetic - Prof. Earl Swartzlander 7) Parallel Computer Architecture - Prof. Derek Chiou 8) Technology for Embedded IoT - Prof. Jonathan Valvano 9) Statistical Methods I - Prof. Matthew Hersh 10) Statistical Methods II - Prof. Matthew Hersh

Enrolled in undergraduate courses on Digital Electronics and Computer Architecture, Digital System Design, Logic Synthesis, VLSI Design, VLSI Design Automation, and Microprocessors to gain foundational knowledge in the domain of VLSI Systems and Computer Architecture