Saharsh Aggarwal
ASIC Design Engineer @ Qualcomm
About
I am a graduate student in Electrical Engineering at Columbia University. I have an experience of 1 year at Ciena where I worked as a Hardware Engineer in the FPGA team. My main task was RTL Design. I am a B.Tech. graduate from Delhi Technological University in Electronics and Communication Engineering. My skills include VLSI, Verilog, Digital Design and Perl. Apart from academics, I'm also a photographer and videographer and have a good experience in Video Editing.
United States
San Diego
Telecommunications
Photography, Verilog, Digital Electronics, Very-Large-Scale Integration (VLSI), Embedded Systems, Lightroom, VHDL, Adobe Premiere Pro, Atmel AVR, ATMega, AVR Studio 4, Proteus, Xilinx Vivado, RTL Design
Experience
ASIC Design Engineer
Qualcomm
San Diego, California, United States
TA for EECS E4321- Digital VLSI
Columbia University
New York, United States
TA for CSEE W6863- Formal Verification of HW/SW Systems
Columbia University
New York, United States
GPU Design Intern
Samsung Electronics
Austin, Texas, United States
• Incorporated the cache subsystem into power flow analysis and reported changes in power usage across different vectors. • Modifying RTL of cache block to increase cache fetch size and see performance benefits.
Hardware Engineer
Ciena
Gurgaon, Haryana, India
Worked on 5166 Ethernet protocol. •Implemented Triple Speed Ethernet Intel FPGA IP in Altera Quartus. •Designed an interface between the Processor and the MAC PCS IP using Verilog. • Collaborated with 4 member team and conducted testing of project on FPGA board. • Produced a detailed document with steps to test a project on FPGA board for future projects.
Product Validation Intern
Cadence
Noida Area, India
• Extracted performance numbers from log files using Perl. • Automated comparison process of 2 .csv files and produced a report on performance deviation of tool. Presented verification team with an in‐depth analysis of tool’s performance under different Testcases. • Built a testbench for injecting “X” in design to check for “X” propagation in System Verilog. Found ”X” induced at one input was propagating through project and suggested corrections to design team.
Winter Intern
Bharat Electronics Limited
Ghāziābād Area, India
• Studied radar system and tested and reviewed PCB Cards of 3D Aslesha Radar, using it’s job sheet and MATLAB. • Steered and Compiled a project report containing details of Aslesha Radar with outputs from Simulink.
Teaching Intern
The Rising People welfare society
New Delhi Area, India
Taught Math and English to a group of 12 underprivileged children.
Education
Columbia University
Electrical Engineering
Delhi Technological University (Formerly DCE)
Electronics and Communications Engineering
Saharsh Aggarwal's Contact Information
Phone
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