Sachin Sreelal

Senior Design Verification Engineer @ Apple

Country

United States

City

Santa Clara

Industry

Semiconductors

Skill

RTL Design, Logic Design, VLSI, Computer Architecture, Network Processors, Verilog, Perl, C, Programming, Embedded Systems, FPGA, ASIC, Testing, Matlab, Linux, C++, Java, Electronics, Circuit Design

Experience

Senior Design Verification Engineer

Apple

2021-12 - Present · 4 yrs 10 mos

GPU Design Verification Engineer

Apple

2019-6 - 2021-12 · 2 yrs 7 mos

United Kingdom

Design Verification Engineer

Apple

2016-6 - 2019-6 · 3 yrs 1 mo

Cupertino, California

Design Verification Intern

Apple

2016-1 - 2016-5 · 5 mos

Cupertino

Verification Engineer Intern

Rocketick Technologies Ltd.

2015-5 - 2015-11 · 7 mos

San Jose

Grader for EE254

USC Ming Hsieh Department of Electrical and Computer Engineering

2015-1 - 2015-5 · 5 mos

Greater Los Angeles Area

Software Engineer

Robert Bosch Engineering and Business Solutions

2012-7 - 2014-7 · 2 yrs 1 mo

Coimbatore Area, India

Predominantly involved in the verification and testing of Electronic control units used in the automotive safety system. Worked as a test-engineer for closed loop control system simulation and analysis of electronic control unit for FIAT OEMs.Component responsible for test script design and tool development in various scripting languages including PERL and VB for integration of newer test sets into the existing environment.