Rushi Mehta
GPU Performance @ Intel
-
United States
Semiconductors
Object Oriented Programming, OVM, System Verilog, C++, Computer Architecture, UVM, x86 ISA, Logic Design, Verilog, MIPS, Open Verification Methodology, SystemVerilog
Experience
GPU Performance
Intel
Santa Clara, California, United States
GPU Performance
AMD
Santa Clara, California, United States
GPU Perf Verification
Qualcomm
Santa Clara, California, United States
GPU Design Verification
Samsung Electronics
San Jose, California
GPU Design Verification
Qualcomm
San Diego
1) Design verification on pixel processing/render backend, cache/compression units, Depth/Color/Stencil pipeline in collabortion with GPU Fixed-Function Cluster DV 2) Shader processor design verification block level and cluster level. 3) Formal equivalence verification between RTL and C++ model using Hector of various GPU sub-blocks 4) Power aware verification using UPF 2.0 including verification of Isolation, retention and power rail collapse sequences/strategies 5) Block/Cluster level verification of power management blocks such as Limit Management, Temperature/Current sensors 6) SystemC Modelling of Power management blocks such as Resource State Controller/Bus Clock Manager for verifying power management sequences.
CPU Design Verification
AMD
Austin, Texas Area
Design Verification of x86 CPU, along with focus on power management verification.
Hardware Engineering Intern
Broadcom
Andover, MA
Design Engineer in Set-Top box SoC team
STMicroelectronics
Education
Texas A&M University
Computer Engineering
National Institute of Technology, Tiruchirappalli
Electronics and Communication
Rushi Mehta's Contact Information
Phone
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