rotem livneh

About

Over the last years I've done Design and Integration, of both macro and chip level, and also designed several modules from scratch. Handled IPs and subsystems based on AXI/APB interfaces, and based on ARM architecture. I participated all design stages, from architecture definition, through module/subsystem design, bug fixes, timing closure, and support verification, synthesis and Silicon Validation teams, and up to APR and ECO fixes.

Country

israel

City

israel

Industry

computer hardware

Skill

verilog, soc, vlsi, rtl design, logic design, functional verification, rtl verification, debugging, systemc, perl, rtl coding, asic, system verilog, integration, static timing analysis, ic, systemverilog

Experience

silicon validation

freescale semiconductor

2012-2 - 2013-1 · 1 yr

Developed environment for silicon validation pattern generation (direct and random), of the SC3900 DSP core sub system.

logic design engineer

freescale semiconductor

2002-1 - 2003-1 · 1 yr 1 mo

Logic design of a Double bus to Single bus Converter.

modeling

freescale semiconductor

2001-1 - 2002-1 · 1 yr 1 mo

Modeling in SystemC for performance and chip architecture.

senior logic design and integration engineer

marvell israel ltd.

2013-1 - 2015-7 · 2 yrs 7 mos

Design and Integration, of both macro and chip level. Handled IPs and subsystems based on AXI/APB interfaces, and based on ARM architecture.

logic design and verification engineer

freescale semiconductor

2010-11 - 2012-2 · 1 yr 4 mos

Logic Design of two blocks in the high speed DSP core sub system: Write Buffer, and Memory Management Unit, Include speed paths fixing, power and timing optimization. Logic Verification using system verilog, of the DSP core sub system.

logic and circuit design and verification

freescale semiconductor

2003-1 - 2009-1 · 6 yrs 1 mo

* Developed memories for caches and ROM: * Logic design of a BIST. * Developed logic verification environment for the memories, include generation of testbench, drivers, monitors, tests, and coverage. * Created behavioral models of the memories. * Circuit design of one block in the memory. * Created Timing Models of the memories. * Run STA (Static Timing Analysis) on the memories.