Rohit Bansal

• Managing DV team responsible for Memory Sub-System Verification of MIPS Based SOC.

• Technical lead for Chip/Platform level verification of a PowerPC compliant Microprocessor and its L2 write-back cache subsystem • Architected a verification methodology that emphasized Block-to-top reuse of verification components using Mentor’s AVM methodology. Designed and developed the Test Bench using SystemVerilog and employed a Random Test Generator developed in co-operation with a third party to create complex PPC assembly tests. • Verified Multiprocessor behavior at Chip level, unearthing complex CPU and L2 cache controller bugs. Worked closely with the design team to bring quick bug resolutions.

• Worked in Systems Verification group (pre-silicon verification) to verify various Storage Subsystems components and I/O ports, bridges and buses in a multiprocessing environment • Worked on testing the failover capability of various bridges and hubs. • Worked closely with the tools team to develop various GUIs to facilitate debugging of simulation failures. • Wrote C++ behavioral model to emulate the hardware functionality and to initialize the chips. Wrote checkers and monitors at both chip and system level.

• Worked with the verification team in verifying Instruction fetch unit of a four-way Simultaneous multi-threaded Alpha Arana Processor. • Used wxWindows to design GUI’s for debugging. • Wrote focus tests using assembly language and performed coverage analysis on them.