Roger Carpenter

Implementation of several generations of Tensor Processing Unit (TPU) chips https://cloud.google.com/tpu Collaborated with Google Deep Mind (GDM) to improve EDA methodology and algorithms Evaluated vendor AI products including Synopsys DSO.ai, Synopsys Fusion-AI, and Cadence Cerebrus Managed team of 15 physical design engineers initially covering ASIC placed netlist handoff now covering full COT flows. Familiar with synthesis, P&R, floorplan, clock/CTS, power analysis, PG/PGA, EMIR, RCE, STA, PV, ESD, interposer Collaborated with internal design/package/system teams, external ASIC vendor and 3PIP (HBM/PCIe/UCIe) partners Reviewed RFQ and SoW documents before getting them approved by ASIC or other vendors.

- Architectural exploration of next machine learning accelerator including matrix multiplication and 2D convolution. - Prototype future machine learning products on FPGA using external vendor for design implementation. - Determine Network on Chip (NoC) and interface IP including HBM, HMC, DDR, PCIe, Interlaken, and CCIX. - Manage 16nm FinFET physical and circuit flows for machine learning accelerator SoC for Artificial Intelligence. - Develop transistor level static timing flow including resources in Sri Lanka and Bangalore. - Lead timing analysis and signoff of greater than 5 GHz 16nm SoC combining custom and ASIC flows. - Prototype SoC including programmable fabric of asynchronous processors, memories, and routing. - Develop methodology and flow for asynchronous synthesis, static timing, and power analysis. - Architect and implement Null Convention Logic multipliers resulting in 3x reduction in power.

- Responsible for design services of sequential clock gating and power pattern generation products. - Design adaptive voltage scaling (AVS) IP including embedded low dropout (LDO) regulators. - Report account engagement strategy, technical execution, investment strategy at board meetings.

- Manage R&D team sprints, scrums. Extend roadmap: ESL, floorplan synthesis, cloud computing. - Partner with IMEC and Qualcomm: Develop architecture and 3D TSV Pathfinding methodology. - Manage and extend customer relationships with presentation, support, training, design services.

- Drove strategic growth of company from single core product to multiple distinct business units. - Galvanize technical sales execution of critical accounts in order to meet quarterly revenue targets. - Manage power gating, hierarchy automation, structured placement, package/chip design teams. - Manage developers and support engineers globally including teams in Bangalore, England, and Germany. - Communicate across business units to integrate separate analog, digital, and analysis products. - Manage patent attorney and roadmap for corporate wide patent portfolio including acquisitions and new filings. - Executive sponsor for major customers in Japan, Taiwan, Europe, and America involving frequent customer visits. - Collaborated with Aplus and AutoESL U.C.L.A. PhD students and Professor Jason Cong, Chief Technology Advisor.

- Managed design groups totaling 15 engineers and up to six projects. Outsourced acquired design. - Project management of 12 unique Ethernet switches across physical, logic, test, and verification. - Established implementation and signoff methodology including clock, DDR, OCV, and crosstalk.

- Established initial physical synthesis flow from logic synthesis through post layout optimization. - Managed team of seven product and design engineers across multiple customers and disciplines. - Customer and internal management of largest tapeout to date at 3Dlabs (Nov 2000 press release)

- Designed and characterized standard cell library. Floorplan, place, and route methodology. - Assisted in design of high speed 4-read/4-write memory and custom datapath arithmetic blocks. - Created signoff methodology including extraction and crosstalk analysis. Implemented clocks.

- Top-down FPGA chip design using Synopsys logic synthesis and Cadence layout synthesis. - I/O cell design, interconnect and test strategies. Look up table vs. antifuse architecture tradeoffs. - Voltage pump and voltage regulator design. Critical path optimization with spice and STA.

- SOI fully depleted device modeling, add back-bias to speedup EEPROM GAL.

- Thesis: Material Characterization Techniques for SOI Devices; Advisor: Prof. Henry I. Smith

- Concentrations in Quantum Physics, Philosophy, and Music. - Member of Track Pole Vault, Ultimate Frisbee, and Crew.