Rittika Roy

• Working with advanced node synthesis of complex high performance SoC designs with extreme low power requirements. • Knowledge in full design flow and methodologies for implementation and IEEE1801 low-power driven implementation. • Experience in RTL design(Verilog/SystemVerilog), System-On-Chip design/integration flow. • Power Analysis and switching activity generation to drive low power optimization during synthesis and PnR. • Utilizing Cadence power analysis software for accurately tracking low power metrics and use cycle based simulated activity for driving synthesis and implementation software to achieve optimal results from activity driven mapping and placement algorithms. • Execute design flows for synthesis/PnR regression runs to assess architectural viability and analyze power-performance-area trade offs for physical design closure. • Scripting and automation for flow execution.

• Building/modifying testbenches, running and analyzing simulations to cover a test plan. • Plan and implement simulation test for digital IP blocks. • Convert simulation vectors to test vectors for silicon validation and production test. • Modify C Code controlling automated test equipment. • Python and Verilog script development to fit new requirements in existing design. • Develop scripts for automation. Generate Fuse Content Files(FCF) for testing team.