Rashid Iqbal

Responsible for supporting Cadence clients in Static Timing Analysis (STA) execution, ensuring efficient timing closure and design optimization. Provide technical expertise in troubleshooting complex timing issues, delivering tailored solutions, and enhancing workflow efficiency. Work closely with customers to maximize the performance of Cadence’s STA tool (Tempus), enabling robust and high-quality semiconductor designs. Collaborate with internal teams to refine methodologies and drive innovation in timing analysis

During his 8 years at Intel Fort Collins, Colorado, Rashid managed Physical Design teams that executed large System-on-Chips (SoCs) in the areas of Servers and Networking. These were large SoC designs with billions of transistors, hundreds of clocks, numerous complex IPs, and their interconnect fabrics. The execution involved over 100 physical design engineers from around the world. Rashid led the physical design execution of entire SoC tapeouts and managed the day-to-day activities in various areas, including full-chip timing, synthesis/Place-and-Route (PnR) of IPs and SoC blocks, full-chip layout convergence, power analysis, formal equivalence, reliability, and post-silicon debug support. Rashid's top strengths within physical design are timing convergence (optimization and verification) of very challenging and difficult to meet timing designs. In timing verification, he has extensive experience in generating constraints for both blocks and full chips, using both top-down and bottom-up approaches. His expertise includes timing triage of internal block paths and full-chip paths for setup and hold times, understanding complex clocking relationships, handling multi-corner scenarios, and managing ECOs. He is adept at creating timing builds at different hierarchies, including hyperscale and libraries, and conducting cross-talk and OCV (On-Chip Variation) analysis. Additionally, he is skilled in bottom-up builds, resolving difficult paths, applying timing exceptions, and performing detailed analysis of critical paths and timing sign-off. In Synthesis and APR (Place-and-Route), Rashid has extensive expertise in handling challenging timing designs and performing various optimizations at different stages of the flow, including synthesis, Floorplanning, placement, clock tree synthesis, and routing. He excels in achieving tighter correlation among these stages and executing clock tree synthesis on complex clock designs with numerous synchronous and asynchronous clocks.

Rashid was the hands-on technical lead and manager of a team of Physical Design Engineers responsible for hardening IP for use in various SoCs. His role involved guiding the team in all areas of physical design, managing schedules and deliveries to the SoC, and collaborating with the IP RTL teams to ensure the IP was fully optimized to its specifications. By working closely with engineers on their daily issues and problems, Rashid was able to step in and resolve any critical bottlenecks in the execution process. The designs he led and managed included network accelerators, PCI controllers, and Ethernet controllers.

As full chip static timing Lead, Rashid taped out multiple chips with 200+ clocks. He developed methodologies, flows, timing, clocks & constraints; ran and analyzed full chip timing in multiple modes and PVTs. Rashid worked with block owners to identify timing and constraints fixes.; carried out spice simulation to explore PVT selection, crosstalk impact and guard-band selection. Rashid carried out full chip floorplan/design-planning work to determine block sizes, their dimensions, pin placement and feedthrus at full chip. He helped block owners to fix their floorplan issues, built full chip layout databases and carried out Formal Equivalence analysis at full chip with feedthrus. He also implemented global clock distribution network and achieved clock convergence for the inter partition clocks. Rashid owned various partitions on critical path for schedule and demonstrated strong expertise in synthesis, place/route and Clock tree synthesis tools. He closed high frequency (GHz) ASIC designs using strong skills with tools, scripting and solid understanding of the underlying circuit/design issues.

As part of the central DA Team, Rashid developed tools, flows and methodologies for synthesis, timing & noise areas. Performed static timing analysis on various projects. Developed TCL/Perl/gmake based highly automated tools to correlate various versions of Synopsys Primetime/SI with Spice for timing and glitch. Rashid was responsible for characterization and qualification of noise libraries for PrimetimeSI.

Designed FPGA systems to implementation motion estimation algirithms. These multi FPGA boards were developed for real time procesing of very high definition video.

Development of FPGA based Real Time Video Processing platforms. Work included selection and analysis of algorithms, development and validation of VHDL/Verilog based hardware on FPGA and then design and testing of the PCBs to demonstrate a working platform. so as part of small team obtained excellent exposure of working on all phases of the design and development.

Developed testbenches to validate IP RTL.