Ran Yang

Design Verification Engineer @ Apple

About

As a Master's student in Electrical and Computer Engineering at Northwestern University, I specialize in digital design verification, with hands-on experience in both FPGA/ASIC verification environments. I am proficient in SystemVerilog, UVM, Verilog, and Python, and skilled with tools such as Cadence Xcelium, Synopsys VCS, Design Compiler, Verdi, and ModelSim

Country

United States

City

San Diego

Industry

Consumer Electronics

Skill

Chip design, chip verification, verification, 通用验证方法学, C 语言, UVM, SystemVerilog 语言, Verilog, Python, C++, Perl, TCL, Linux

Experience

Design Verification Engineer

Apple

2025-7 - Present · 1 yr 3 mos

San Diego, California, United States

Design Verification Engineer

Hisilicon

2024-7 - 2024-9 · 3 mos

Implemented four-way MIMO packet processing and forwarding at an FP4 line rate, supporting packet sizes ranging from 18 bytes to 1024 bytes. Conducted RTL design using Verilog and employed RR scheduling algorithm for efficient input-output arbitration. Optimized ASIC chip design to meet stringent PPA targets through RTL-level enhancements. Applied advanced techniques including pipeline insertion, barrel shifter, and tunnel shifter, resulting in 13% timing improvement and a 10% power reduction verified by Synopsys Design Compiler Developed an UVM-based verification environment, defined and decomposed detailed test points, generated comprehensive functional and code coverage metrics, and performed daily regression tests using TCL, successfully achieving 100% coverage to ensure functional correctness of the design.