ramesh saminathan

staff engineer

About

- Strong knowledge in Mixed Signal product testing like ADC / DAC / PLL using ATE. - Advantest 93000, Teradyne Flex, ASL3K RF. - Pre-Silicon and Post-Silicon Test program development for Single site and multi site solutions, Debug at wafer level / Package level, Characterization across PVT (Process/Voltage/Temp), Correlation across different FABS / Sites / Load Board, Test Program release to production. - Statistical Analysis Tool: Data power and SEDana - Test Time Reduction with utilizing ATE feature like SMC Hidden upload (SmartCalc), Concurrency between core in SOC chips, Optimizing test program. - Yield improvement, Reduce retest rate using OT plus tool. - Reduce testing cost for Analog devices: By implementing basic test cases in Wafer level without losing coverage, Implementing Analog on Digital for ADC's (Testing ADC devices using Digital channel instead of AWG). - Version control: SVN, CVS - Test Program integration using MFH (Master File Handling). - Efficiency improvement: Automated repetitive tasks. - Scripts: Perl, VBA, C++ - Able to support remotely.

Country

singapore

City

singapore

Industry

semiconductors

Skill

test engineering, mixed signal, testing, verigy 93k, analog, debugging, test program development, product engineering, semiconductors, schematic capture, test development, characterization, perl, orcad, ate, datapower, test time reduction, ic, soc

Experience

staff engineer

marvell semiconductor

2020-5 - Present · 6 yrs 5 mos

senior ate test engineer

marvell semiconductor

2016-10 - Present · 10 yrs

test engineer

tessolve semiconductor pvt ltd (tessolvedts inc)

2008-7 - 2012-3 · 3 yrs 9 mos

senior test engineer

tessolve semiconductor pvt ltd (tessolvedts inc)

2012-4 - 2013-3 · 1 yr

* Handled individual blocks in MSM SoC chips and working with team in Verigy 93K. * Involved in test program development in Verigy 93k for Wafer sort and Final test. * Involved in Load board debug during bringing up. * Analyzed characterization data and shared with bench team. Created correlation report for multi site load board solutions.

test lead

tessolve semiconductor pvt ltd (tessolvedts inc)

2014-7 - 2014-7 · 1 mo

Working as Mixed Signal Lead (ADC/DAC/PLL/LDO) for two MSM SoC chips parallel in customer site using Advantest 93000 tester with smartest version of 7.2.2.4. - Monitoring yield fallout for Mixed signal blocks in weekly, finding the root cause for the yield fallout, fixing the issues in smartest way to avoid yield fallout in future. - Reducing retest rate by analyzing production yield in weekly. Finding why retest rate is higher for some test cases whether its due to Hardware issues (like Load board, tester), test case instability, any FAB related or any lot issues. - Used Optimal Test Plus tool for monitoring Yield & retest rate. - Involving in Test time reduction for Mixed signal cores to reduce testing cost in mass production by implementing SmartCalc, Concurrency, combining two test cases into one test case, reducing sample size, reducing test cases based on DPPM and optimizing the setups.