ramakrishnan gt

staff rfic layout designer

About

A Mixed signal layout designer with strong passion for coding and 9+ years of Analog/RF layout experience.  Involved in various automation of analog layout using SKILL, Diva, Perl.  Familiar with text grabbing using wget, sed, and awk from websites and large text files.  Responsible for layout of RF Data Convertors in 28nm from layout of circuit feasibility to GDS delivery guiding a team size of 5+.  Co-ordinating the PD team in integration of complex RF blocks which involves custom clock channels.  High speed standard cell library development for RF projects in 28nm  Worked on technodes ranging from 65nm to 28nm.  Handled multiple deliveries like GDS, LEF, noise models.

Country

india

City

udupi

Industry

semiconductors

Skill

cadence skill, cadence virtuoso, parasitic extraction, drc, lvs, virtuoso layout editor, floorplanning, rf, lna, verilog, mixed signal, analog, cadence, semiconductors

Experience

staff rfic layout designer

maxlinear

2016-4 - Present · 10 yrs 6 mos

Staff RFIC Layout Designer at MaxLinear

rf layout designer @ qualcomm

karmic design private ltd

2013-2 - 2013-10 · 9 mos

* Wireless transmitter receiver sub modules. * Low Noise Amplifier * WLAN DAC - 14 bit Calibrated DAC

analog and rf layout designer @ texas instruments

karmic design private ltd

2006-6 - 2012-12 · 6 yrs 7 mos

* Module layout design in following in 65nm, 45nm and 32nm technologies for OMAP, SERDES, FM * High performance DAC, Calibrated DAC. * Clock Generators (PLL), crystal oscillator drivers and RC oscillators. * Transmitter and Receiver sub modules. * Millimeter wave Transceiver (PLL, MIXER, Op-Amp, DAC). * Proven ability in delivering the work from module level to chip with high quality in the following projects. * LDO * RF clock domain * Terahertz project * WLAN DAC, TXDAC and Feedback DAC * Handful experience in SKILL programming to ease the layout work.

senior ms layout designer

pmc-sierra

2013-11 - 2016-4 · 2 yrs 6 mos

* Responsible for delivering layout of RF data converters starting from circuit feasibility till final GDS delivery. Guiding a team size of 5+ members. * Projects: * Clock generator * RFADC * High speed standard cell library * RFDAC * Worked on various tool evaluations before adopting them to the team.