Swati Ramachandran

--Worked on development and deployment of a software tool that uses Machine Learning for optimizing functional verification bottlenecks like bug discovery and coverage closure. --Hands-on experience with Data Extraction, Transformation, Loading (ETL) Processes --Leveraged Dask Distributed with Prefect to deploy over distributed cluster --Involved in developing and maintaining CI/CD flows using Jenkins

Worked on optimising CPU Verification techniques using Machine Learning algorithms. This included: --Understanding and formulating the problem statement (faster bug detection) --Data exploration --Choosing potential algorithms (both supervised and unsupervised) and working on train-validate-test scheme --Experimental results --Final deployment of a command-line tool (developed in Python), which incorporates the chosen model for selecting efficient tests

--Worked on UVM and SystemVerilog projects for various customers, which included adoption of UVM REG Verification, architecting effective testbenches and reuse from block to SOC level --Deep understanding of industry standard protocols like DDRx, LPDDRx, AHB, APB, I2C, UART etc. --Worked on verifying UART and OSPI blocks in a complex automotive based SOC --Worked on support of Memory Models and Verification IP for various customers. The role involved driving new technologies and business opportunities --Drove the adoption of debug solutions across various customers. Demonstrated 4X increase in productivity in testbench debug -- Worked on Embedded Software debug for HW/SW co-debug --Worked on a novel MDV approach to instrument coverage over testbench for identifying coverage holes quicker --Drove the adoption of SV 2012 Real Number models (RNM) for mixed signal verification. --Delivered several successful SystemVerilog, advanced UVM and UVM REG trainings for various customers --Published several articles for Cadence Online Support and Cadence blogs --Co-authored the following papers for CDNLive: Code Coverage On System Verilog Testbench As A Verification Signoff Metric Verification Management & Regression Productivity Improvement using vManager Accelerate Verification Productivity using Indago Debug Analyzer Usage of SV 2012 RNM with UVM for Enhanced Mixed-Signal Verification: A case study --Links to articles/papers: https://community.cadence.com/cadence_blogs_8/b/fv/posts/searching-through-a-complex-design-dfs-to-the-rescue https://www.cadence.com/content/cadence-www/global/en_US/home/cdnlive/india-2015/proceedings.html https://www.cadence.com/content/cadence-www/global/en_US/home/cdnlive/india-2016/proceedings.html

--Worked as a verification engineer in the Verification IP domain on memory protocols (DDR2, DDR3, LPDDR, LPDDR2, LPDDR3) using standard methodologies like OVM and UVM. --Responsible for creating exhaustive test plans for all interfaces to achieve 100% functional coverage using UVM. --Created reusable and configurable generic sequences for all protocols. --Coded and tested all assertions using TDD approach for DDR2 and DDR3. --Wrote BFM code for few features like write leveling, ODT etc. for DDR2 and DDR3. --Automated the process for verification of coverage and assertions by introducing a self checking mechanism.

--Worked on verification of LC3 microcontroller using SystemVerilog --Wrote functional coverage model to achieve 100% coverage --Wrote SystemVerilog assertions to verify correctness of the design