Raj Mareps
Founder @ Tsavorite Scalable Intelligence
About
Product and Engineering Leader with extensive experience in Design of High-Performance Computing Solutions, including Microprocessors, SoC/IP subsystems for Servers, Custom Silicon and ASIC Systems for AI/ML accelerators.
United States
Cupertino
Computer Hardware
EDA, Semiconductors, ASIC, VLSI, Integrated Circuit Design, IC, Physical Design, SoC, Static Timing Analysis, Semiconductor Industry, Embedded Systems, Perl, Computer Architecture, Simulations, Integration, Application-Specific Integrated Circuits (ASIC), System on a Chip (SoC)
Experience

Product Manager
Santa Clara, CA
Knights Landing (Xeon Phi Processor) was launched in 2016. Responsible for overall Si Design (from Concept through Release): * Planning - Product Road maps, Milestone Definition, Schedule Models. * Execution - Work flow & Resource Management, Communication * Stakeholder Management - Influence Platform stakeholders (Arch, SW/FW, Pre&Post-Si Verification,Boards/Mfg, Marketing) * Operations - Initiatives to foster culture of Learning & Collaboration

Senior Design Manager
Santa Clara
• Managed post-Si and product launch of Knights Ferry (1st gen Intel MIC- Xeon Phi™ ) to enable HW/SW co-design & validation, and SW readiness with major OEM and Independent SW vendors (ISVs). • Managed GDDR5 Memory Controller IP Development and SOC Integration
Raj Mareps's Contact Information
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