Raj Mareps

Raj Mareps

Founder @ Tsavorite Scalable Intelligence

About

Product and Engineering Leader with extensive experience in Design of High-Performance Computing Solutions, including Microprocessors, SoC/IP subsystems for Servers, Custom Silicon and ASIC Systems for AI/ML accelerators.

Country

United States

City

Cupertino

Industry

Computer Hardware

Skill

EDA, Semiconductors, ASIC, VLSI, Integrated Circuit Design, IC, Physical Design, SoC, Static Timing Analysis, Semiconductor Industry, Embedded Systems, Perl, Computer Architecture, Simulations, Integration, Application-Specific Integrated Circuits (ASIC), System on a Chip (SoC)

Experience

Tsavorite Scalable Intelligence

Founder

Tsavorite Scalable Intelligence

LinkedIn
2023-11 - Present · 2 yrs 11 mos

San Francisco Bay Area

Intel

Product Manager

Intel

LinkedIn
2021-2 - 2023-10 · 2 yrs 9 mos

Product Manager - Intel Xeon Servers and Workstation Segment. Successfully launched Sapphire Rapids (4th Gen Intel® Xeon®) Scalable Server and Workstation product.

Intel

Director - Compute Accelerators and Prototype Solutions

Intel

LinkedIn
2018-1 - 2021-1 · 3 yrs 1 mo

Data Center System Platforms and Prototype solutions for Deep Learning and High-Performance Compute Products. FPGA and Emulation based Hardware and Software co-development, System Validation

Intel

New Business Initiative

Intel

LinkedIn
2016-1 - 2017-12 · 2 yrs

Enabling Intel's foray into Deep Learning (Machine Learning) and other new opportunities in High Performance Computing, Data Center Network, 5G Wireless Base station markets with IA (x86) and Custom Silicon solutions

Intel

Business Operations Manager

Intel

LinkedIn
2015-6 - 2017-1 · 1 yr 8 mos

Implemented Transformational Initiatives for Organizational Growth and Learning. R&D Budget, Forecasting. Silicon Design and Development Engineering Execution efficiencies.

Intel

Product Manager

Intel

LinkedIn
2012-6 - 2015-5 · 3 yrs

Santa Clara, CA

Knights Landing (Xeon Phi Processor) was launched in 2016. Responsible for overall Si Design (from Concept through Release): * Planning - Product Road maps, Milestone Definition, Schedule Models. * Execution - Work flow & Resource Management, Communication * Stakeholder Management - Influence Platform stakeholders (Arch, SW/FW, Pre&Post-Si Verification,Boards/Mfg, Marketing) * Operations - Initiatives to foster culture of Learning & Collaboration

Intel

Technical Marketing - Notebook(Client) Segment

Intel

LinkedIn
2010-11 - 2012-5 · 1 yr 7 mos

Tech Marketing - Notebook (Client) Segment

Intel

Senior Design Manager

Intel

LinkedIn
2007-1 - 2010-9 · 3 yrs 9 mos

Santa Clara

• Managed post-Si and product launch of Knights Ferry (1st gen Intel MIC- Xeon Phi™ ) to enable HW/SW co-design & validation, and SW readiness with major OEM and Independent SW vendors (ISVs). • Managed GDDR5 Memory Controller IP Development and SOC Integration

Intel

ASIC Design Lead

Intel

LinkedIn
2006-1 - 2006-12 · 1 yr

Santa Clara

•Managed physical design & integration responsibilities for Si Interposer Bridge (65nm ASIC implementation), used for high speed I/O HVM testing on low-cost/speed testers (ATE) .

Intel

CPU Design

Intel

LinkedIn
2000-12 - 2005-12 · 5 yrs 1 mo

San Francisco Bay Area

• Progressive roles leading to Design Manager on various generations of Intel CPU Products (90nm-45nm)

Synopsys Inc

Application Engineer

Synopsys Inc

LinkedIn
2000-1 - 2000-11 · 11 mos

San Francisco Bay Area

Startup acquired by Synopsys in 2002 EDA Tool Support

Raj Mareps's Contact Information

Email

******@***.com

Phone

(**) *** ****

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