Rahul Govindan

GPU Memory hierarchy and interconnects design

TA under Prof Pannuto, for CSE 141 - Intro to Computer Architecture

Internship with the NVLink modelling team, worked on building architectural models of the NVLink and NVSwitch, which enable the high-speed interconnect of multi-GPU systems. Helped bring-up & debug new GPU/Switch configurations in simulation.

• Worked on the FPGA prototyping of SoC designs, involving design partition, RTL code migration, RTL synthesis, and FPGA implementation. Obtained in-depth knowledge of the SoC design, and on-chip hardware reset flow. • Utilized the Synopsys Zebu emulator, and Synopsys VCS tool to support debug on the FPGA platform. • Used knowledge of python and tcl to create tools improving the performance and the user experience of the platform, and partnered with the AI CoE team to automate SoC design partition, reducing design bring-up time on FPGA by 50%. • Promoted and received multiple internal recognition awards for work achievements.

• Worked on improving the debug capabilities of FPGA based prototyping by constructing a debug data capture system that aggregates data, transmits it over a serial link, and stores it in a DDR SRAM. • Created an Avalon Streaming System using System Verilog for data transfer on a multi-FPGA platform • Learnt the FPGA prototyping flow and developed scripts for analyzing SoC side-band network data.

Learnt the basics of industrial automation and details about Distributed Control Systems (Foxboro) and Emergency shutdown systems (Triconex).

Created an android app for promoting Tourism in TN, along with a website and database for storing and modifying data related to the app. Used xml, Java, html, JavaScript, php and SQL.