PUNITH B T

Senior DFT Engineer @ Sykatiya Technologies Pvt Ltd

About

A result oriented professional with 5+ years experience in Design for Testability (DFT) and Validation on ATE (Verigy 93k)

Country

India

City

Bengaluru

Industry

Semiconductors

Skill

Verigy 93K, Scan Insertion, Test Program Development, Test Engineering, Spyglass, Automatic Test Pattern Generation (ATPG), Program Development, DFT, Testing

Experience

Senior DFT Engineer

Sykatiya Technologies Pvt Ltd

2020-5 - Present · 6 yrs 5 mos

India

Spyglass, pattern generation, coverage improvement, Simulation with and without SDF. ATE - Pattern deliverables, ATE support, data analysys (VMIN/FMAX) and testtime reduction. Client - Rambus (1.6 years) Spyglass connectivity checks and spyglass DRC fix. Client Google (3 Months) Methodology Development for MBIST, ATPG, Implementation of SSN and IJTAG. Client : Marvell (present)

DFT Engineer

Tessolve

2017-1 - 2020-5 · 3 yrs 5 mos

Spyglass, Scan Insertion, ATPG Coverage Improvement and Pattern Generation. Client - Intel (2 years) Scan Implementation, LEC (Formal verification), STA report generation and analysis, Coverage improvement, pattern generation and Simulation. Client - Qualcomm

ATE Test Engineer

Tessolve

2013-7 - 2016-12 · 3 yrs 6 mos

Bangalore

Digital (ATPG, TDF, PDF, IDDq), Functional and Memory testing. Production Test program development, Testime Reduction activities Tester - Verigy 93k Client - Qualcomm