Preeth Sivakumar, PhD

NPI and process development for new conformal coatings (Collaborator: Honeywell FM&T, Kansas City) • Researched and developed two new nano-composite based conformal coating that can reduce the existing product cost by 75% and processing cost by 60% without compromising the performance • Developed and reported scale-up procedures for transferring the processing of two new nano-composite based conformal coatings on PCB from research and development laboratory to production • Developed characterization methodologies for new conformal coatings by designing and building proper fixtures for the test • Designed and conducted novel experiments in microstructural analysis and mechanical testing (nano-micro-macro scale) to understand the structure-property relationships of new thin-film coatings • Characterized the coated coupons and components under various environmental and reliability testing conditions, such as mechanical loading, thermal and moisture stressing • Developed and reported Six-Sigma and Lean tools like process map, DFMA, PFMEA, flowchart for newly defined products and DOE, and FMEA to identify possible wastes in production processes and improve in-process quality • Designed and documented the control plans for high-risk failure modes in PFMEA • Troubleshot and resolved the issues in various lab equipment by working with the suppliers • Acquired experience in process development and optimization, materials characterization, failure analysis techniques, designing the list of experiments using DOE techniques and in-depth data analysis

Process optimization for picking ultra-thin die from wafer tape (Collaborator: Universal Instruments Corp, Conklin) • Investigated different design parameters for an automated die picking process to reduce the defects and increase the yield • Simulated the stress and deformation of the 15nm die during its picking from wafer tape to ensure good device yield and reliability • Validated the model using the DIC measurement of the ultra-thin die picking process • Proposed and documented a process design that can reduce the stress on 15µm die by 83% while picking it from wafer tape

Quantitative accelerated life testing of Flip-Chip assembly (Collaborator: Analog Devices Inc, Boston) • Studied the accelerated life testing under a high-temperature environment for new flip-chip assembly used in automotive electronics • Evaluated the possible mechanisms that might cause the failure of the flip-chip assembly during its service • Documented the effects of the addition of different alloying elements to the solder balls during the aging of the flip-chip package • Characterized the microstructure developments at different interfaces due to the presence of different substrate materials • Conducted different experiments to understand the changes in mechanical properties at the interface and bulk solder ball during accelerated aging

Process development for post-crash investigation of memory devices (Collaborator: NTSB, US) • Developed and reported a process for 2D and 3D x-ray inspection of flash memory modules during the post-crash investigation without affecting the data due to x-ray exposure • Analyzed the flash memory device failures when exposed to various operating conditions to determine the failure mode and root cause • Proposed, developed, and evaluated a new process to retrieve data from a physically damaged memory device and documented the new procedure for data retrieval from damaged the memory devices • Projected in the reduction of 33% data loss during the x-ray inspection and 100% data retrieval from a damaged memory device

Materials optimization for die-attach (Collaborator: Dielectric Laboratories, Cazenovia) • Investigated the effect of different barrier layer materials to increase the liquid state duration of Au rich Au-Sn solder • Proposed a design to increase the liquid state duration of solder by 3 times for attaching multiple devices during the die-attach process • Designed and built special set-up and test fixtures for testing under potential real-life operation modes

Failure analysis study of various seatbelt parts (Pillar loop, Locking bar, Locking ring) • Achievements: Doubled the production speed by isolating the root cause of problems • Experience of designing and did statistical data analysis to provide risk assessments of the design • Results from the reliability tests were analyzed by FMEA, VSM, Ishikawa diagram and process mapping Poster presentation: • Failure analysis of metallic and non-metallic seat belt parts - Quanta 2012, Anna University, Chennai